From: Eddie Hung Date: Wed, 21 Aug 2019 01:27:16 +0000 (-0700) Subject: Add (* abc_arrival= *) doc X-Git-Tag: working-ls180~1075^2^2~54 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4cd1d21bfe412e9c6edb8aa74c19ee57370c56c4;p=yosys.git Add (* abc_arrival= *) doc --- diff --git a/README.md b/README.md index fe30348eb..63cefaf26 100644 --- a/README.md +++ b/README.md @@ -414,6 +414,11 @@ Verilog Attributes and non-standard features `abc9` to preserve the integrity of carry-chains. Specifying this attribute onto a bus port will affect only its most significant bit. +- The port attribute ``abc_arrival`` specifies an integer (for output ports + only) to be used as the arrival time of this sequential port. It can be used, + for example, to specify the clk-to-Q delay of a flip-flop for consideration + during techmapping. + Non-standard or SystemVerilog features for formal verification ==============================================================