From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 31 Dec 2019 23:24:02 +0000 (-0800)
Subject: FDCE ports to be alphabetical
X-Git-Tag: working-ls180~881^2^2~38
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4cdba00e25d892b90c0ee48716c17dec60e472db;p=yosys.git

FDCE ports to be alphabetical
---

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 4d20e1d2c..982ccad72 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -405,10 +405,10 @@ module FDCE (
   (* invertible_pin = "IS_C_INVERTED" *)
   input C,
   input CE,
-  (* invertible_pin = "IS_D_INVERTED" *)
-  input D,
   (* invertible_pin = "IS_CLR_INVERTED" *)
-  input CLR
+  input CLR,
+  (* invertible_pin = "IS_D_INVERTED" *)
+  input D
 );
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;