From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 1 Jul 2022 15:10:02 +0000 (+0100)
Subject: clarify quirks
X-Git-Tag: opf_rfc_ls005_v1~1420
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4ce3cf14c05b1ca611baaa10ae27c87a07513335;p=libreriscv.git

clarify quirks
---

diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn
index 448d6b0b6..bd8708850 100644
--- a/openpower/sv/svp64_quirks.mdwn
+++ b/openpower/sv/svp64_quirks.mdwn
@@ -11,8 +11,8 @@ as a concept became popular.
    are the sole exclusive bedrock.
 2. No scalar instruction ever deviates in its encoding or meaning
    just because it is prefixed (semantic caveats below)
-3. A hardware-level for-loop makes vector elements 100% synonymous
-   with scalar instructions (the suffix)
+3. A hardware-level for-loop (the prefix) makes vector elements
+   100% synonymous with scalar instructions (the suffix)
 
 How can a Vector ISA even exist when no actual Vector instructions
 are permitted to be added? It comes down to the strict RISC abstraction.