From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 18 Oct 2019 08:26:47 +0000 (+0200)
Subject: soc/cores/icap/ICAPBitstream: always keep fifo.source.ready to 1
X-Git-Tag: 24jan2021_ls180~900
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4cf346a1d4d258949894f51f8b41665a1b943d5e;p=litex.git

soc/cores/icap/ICAPBitstream: always keep fifo.source.ready to 1
---

diff --git a/litex/soc/cores/icap.py b/litex/soc/cores/icap.py
index 6c312dda..5d7626b1 100644
--- a/litex/soc/cores/icap.py
+++ b/litex/soc/cores/icap.py
@@ -112,9 +112,9 @@ class ICAPBitstream(Module, AutoCSR):
         self._csib = _csib = Signal(reset=1)
         self._i    =    _i = Signal(32, reset=0xffffffff)
         self.comb += [
+            fifo.source.ready.eq(1),
             If(fifo.source.valid,
                 _csib.eq(0),
-                fifo.source.ready.eq(1),
                 _i.eq(fifo.source.data)
             )
         ]