From: Luke Kenneth Casson Leighton Date: Thu, 28 May 2020 10:27:20 +0000 (+0100) Subject: remove trick of not setting SO X-Git-Tag: div_pipeline~774 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4cf5b246048420f8a5d7b6942aac589e9abf4f2f;p=soc.git remove trick of not setting SO --- diff --git a/src/soc/fu/alu/output_stage.py b/src/soc/fu/alu/output_stage.py index 1ee3a4a0..f054e3ec 100644 --- a/src/soc/fu/alu/output_stage.py +++ b/src/soc/fu/alu/output_stage.py @@ -32,10 +32,7 @@ class ALUOutputStage(CommonOutputStage): # copy overflow and sticky-overflow comb += self.o.xer_so.data.eq(self.so) - # SO is to be set - however to save regfile port requests, only set - # if the data actually changes. only possible due to pass-thru - with m.If(self.i.xer_so.data != self.so): - comb += self.o.xer_so.ok.eq(op.oe.oe & op.oe.oe_ok) + comb += self.o.xer_so.ok.eq(op.oe.oe & op.oe.oe_ok) comb += self.o.xer_ov.data.eq(ov) comb += self.o.xer_ov.ok.eq(op.oe.oe & op.oe.oe_ok) # OV/32 is to be set