From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 26 Jun 2019 18:23:57 +0000 (-0700)
Subject: Cleanup abc_box_id
X-Git-Tag: working-ls180~1208^2~70
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4d0014d1b1a9e747389172b94a45a7dd4af86c6b;p=yosys.git

Cleanup abc_box_id
---

diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 67d1ffb1e..b1c24ed24 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -16,7 +16,7 @@ MUXF8 2 1 3 1
 
 # Inputs: I0 I1 I2 I3 S0 S1
 # Outputs: O
-MUXF78 10 1 6 1
+MUXF78 3 1 6 1
 190 193 217 223 296 273
 
 # CARRY4 + CARRY4_[ABCD]X
@@ -25,7 +25,7 @@ MUXF78 10 1 6 1
 #   (NB: carry chain input/output must be last
 #        input/output and have been moved there
 #        overriding the alphabetical ordering)
-CARRY4 3 1 10 8
+CARRY4 4 1 10 8
 482 -   -   -   -   223 -   -   -   222
 598 407 -   -   -   400 205 -   -   334
 584 556 537 -   -   523 558 226 -   239
@@ -38,20 +38,20 @@ CARRY4 3 1 10 8
 # SLICEM/A6LUT
 # Inputs: A0 A1 A2 A3 A4 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 WCLK WE
 # Outputs: DPO SPO
-RAM32X1D 4 0 13 2
+RAM32X1D 5 0 13 2
 -   -   -   -   -   - 631 472 407 238 127 - -
 631 472 407 238 127 - -   -   -   -   -   - -
 
 # SLICEM/A6LUT
 # Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
 # Outputs: DPO SPO
-RAM64X1D 5 0 15 2
+RAM64X1D 6 0 15 2
 -   -   -   -   -   -   - 642 631 472 407 238 127 - -
 642 631 472 407 238 127 - -   -   -   -   -   -   - -
 
 # SLICEM/A6LUT + F7[AB]MUX
 # Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
 # Outputs: DPO SPO
-RAM128X1D 6 0 17 2
+RAM128X1D 7 0 17 2
 -    -    -   -   -   -   -   - 1009 998 839 774 605 494 450 - -
 1047 1036 877 812 643 532 478 - -    -   -   -   -   -   -   - -
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index e3391da40..58e9c74d5 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -170,7 +170,7 @@ module MUXF8(output O, input I0, I1, S);
 endmodule
 
 `ifdef _ABC
-(* abc_box_id = 10, lib_whitebox *)
+(* abc_box_id = 3, lib_whitebox *)
 module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
   assign O = S1 ? (S0 ? I3 : I2)
                 : (S0 ? I1 : I0);
@@ -181,7 +181,7 @@ module XORCY(output O, input CI, LI);
   assign O = CI ^ LI;
 endmodule
 
-(* abc_box_id = 3, abc_carry, lib_whitebox *)
+(* abc_box_id = 4, abc_carry, lib_whitebox *)
 module CARRY4((* abc_carry_out *) output [3:0] CO, output [3:0] O, (* abc_carry_in *) input CI, input CYINIT, input [3:0] DI, S);
   assign O = S ^ {CO[2:0], CI | CYINIT};
   assign CO[0] = S[0] ? CI | CYINIT : DI[0];
@@ -289,7 +289,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
 endmodule
 
-(* abc_box_id = 4, abc_scc_break="D" *)
+(* abc_box_id = 5, abc_scc_break="D" *)
 module RAM32X1D (
   output DPO, SPO,
   input  D, WCLK, WE,
@@ -307,7 +307,7 @@ module RAM32X1D (
   always @(posedge clk) if (WE) mem[a] <= D;
 endmodule
 
-(* abc_box_id = 5, abc_scc_break="D" *)
+(* abc_box_id = 6, abc_scc_break="D" *)
 module RAM64X1D (
   output DPO, SPO,
   input  D, WCLK, WE,
@@ -325,7 +325,7 @@ module RAM64X1D (
   always @(posedge clk) if (WE) mem[a] <= D;
 endmodule
 
-(* abc_box_id = 6, abc_scc_break="D" *)
+(* abc_box_id = 7, abc_scc_break="D" *)
 module RAM128X1D (
   output       DPO, SPO,
   input        D, WCLK, WE,