From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 20 Feb 2021 22:13:20 +0000 (+0000)
Subject: add some debug checking to get_pdecode_cr_out
X-Git-Tag: convert-csv-opcode-to-binary~189
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4d05968e416d53c77daf644db66f24bf5d140ee1;p=soc.git

add some debug checking to get_pdecode_cr_out
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 65da6741..4a4935f2 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -370,12 +370,14 @@ def get_pdecode_cr_out(dec2, name):
     out_sel = yield op.cr_out
     out_bitfield = yield dec2.dec_cr_out.cr_bitfield.data
     sv_cr_out = yield op.sv_cr_out
+    spec = yield dec2.crout_svdec.spec
     # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
     out = yield dec2.e.write_cr.data
     o_isvec = yield dec2.o_isvec
     print ("get_pdecode_cr_out", out_sel, CROutSel.CR0.value, out, o_isvec)
     print ("    sv_cr_out", sv_cr_out)
     print ("    cr_bf", out_bitfield)
+    print ("    spec", spec)
     # identify which regnames map to out / o2
     if name == 'CR0':
         if out_sel == CROutSel.CR0.value:
diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 6cf06f34..85f7b32d 100644
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -1071,6 +1071,9 @@ class PowerDecode2(PowerDecodeSubset):
         m.submodules.o_svdec = o_svdec = SVP64RegExtra()
         m.submodules.o2_svdec = o2_svdec = SVP64RegExtra()
 
+        # debug access to crout_svdec (used in get_pdecode_cr_out)
+        self.crout_svdec = crout_svdec
+
         # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
         reg = Signal(5, reset_less=True)