From: Eric Engestrom <eric.engestrom@intel.com>
Date: Fri, 15 Jun 2018 16:58:17 +0000 (+0100)
Subject: radv: fix bitwise check
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4d08c1e7d15f7d2c0a406cf1c79314511778b38f;p=mesa.git

radv: fix bitwise check

Fixes: 922cd38172b8a2bc286bd "radv: implement out-of-order rasterization when it's safe on VI+"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
---

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index ccbcbbadd55..113622bb0ce 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -622,7 +622,7 @@ radv_blend_check_commutativity(struct radv_blend_state *blend,
 		(1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
 
 	if (dst == VK_BLEND_FACTOR_ONE &&
-	    (src_allowed && (1u << src))) {
+	    (src_allowed & (1u << src))) {
 		/* Addition is commutative, but floating point addition isn't
 		 * associative: subtle changes can be introduced via different
 		 * rounding. Be conservative, only enable for min and max.