From: Anton Blanchard <anton@linux.ibm.com>
Date: Thu, 19 Sep 2019 10:22:36 +0000 (+1000)
Subject: Reformat CR file
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4d0afa3a6dd35dd5c137d38c04b2458b24924574;p=microwatt.git

Reformat CR file

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
---

diff --git a/cr_file.vhdl b/cr_file.vhdl
index 8ad8570..fa56dd9 100644
--- a/cr_file.vhdl
+++ b/cr_file.vhdl
@@ -6,55 +6,55 @@ library work;
 use work.common.all;
 
 entity cr_file is
-	port(
-		clk   : in std_logic;
+    port(
+        clk   : in std_logic;
 
-		d_in  : in Decode2ToCrFileType;
-		d_out : out CrFileToDecode2Type;
+        d_in  : in Decode2ToCrFileType;
+        d_out : out CrFileToDecode2Type;
 
-		w_in  : in WritebackToCrFileType
-	);
+        w_in  : in WritebackToCrFileType
+        );
 end entity cr_file;
 
 architecture behaviour of cr_file is
-	signal crs : std_ulogic_vector(31 downto 0) := (others => '0');
-	signal crs_updated : std_ulogic_vector(31 downto 0) := (others => '0');
+    signal crs : std_ulogic_vector(31 downto 0) := (others => '0');
+    signal crs_updated : std_ulogic_vector(31 downto 0) := (others => '0');
 begin
-	cr_create_0: process(all)
-		variable hi, lo : integer := 0;
-		variable cr_tmp : std_ulogic_vector(31 downto 0) := (others => '0');
-	begin
-		cr_tmp := crs;
-
-		for i in 0 to 7 loop
-			if w_in.write_cr_mask(i) = '1' then
-				lo := i*4;
-				hi := lo + 3;
-				cr_tmp(hi downto lo) := w_in.write_cr_data(hi downto lo);
-			end if;
-		end loop;
-
-		crs_updated <= cr_tmp;
-	end process;
-
-	-- synchronous writes
-	cr_write_0: process(clk)
-	begin
-		if rising_edge(clk) then
-			if w_in.write_cr_enable = '1' then
-				report "Writing " & to_hstring(w_in.write_cr_data) & " to CR mask " & to_hstring(w_in.write_cr_mask);
-			end if;
-			crs <= crs_updated;
-		end if;
-	end process;
-
-	-- asynchronous reads
-	cr_read_0: process(all)
-	begin
-		-- just return the entire CR to make mfcrf easier for now
-		if d_in.read = '1' then
-			report "Reading CR " & to_hstring(crs_updated);
-		end if;
-		d_out.read_cr_data <= crs_updated;
-	end process;
+    cr_create_0: process(all)
+        variable hi, lo : integer := 0;
+        variable cr_tmp : std_ulogic_vector(31 downto 0) := (others => '0');
+    begin
+        cr_tmp := crs;
+
+        for i in 0 to 7 loop
+            if w_in.write_cr_mask(i) = '1' then
+                lo := i*4;
+                hi := lo + 3;
+                cr_tmp(hi downto lo) := w_in.write_cr_data(hi downto lo);
+            end if;
+        end loop;
+
+        crs_updated <= cr_tmp;
+    end process;
+
+    -- synchronous writes
+    cr_write_0: process(clk)
+    begin
+        if rising_edge(clk) then
+            if w_in.write_cr_enable = '1' then
+                report "Writing " & to_hstring(w_in.write_cr_data) & " to CR mask " & to_hstring(w_in.write_cr_mask);
+            end if;
+            crs <= crs_updated;
+        end if;
+    end process;
+
+    -- asynchronous reads
+    cr_read_0: process(all)
+    begin
+        -- just return the entire CR to make mfcrf easier for now
+        if d_in.read = '1' then
+            report "Reading CR " & to_hstring(crs_updated);
+        end if;
+        d_out.read_cr_data <= crs_updated;
+    end process;
 end architecture behaviour;