From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 31 Oct 2014 11:58:36 +0000 (+0100)
Subject: bus/csr: add configurable address_width (needed more than 32 modules with CSR)
X-Git-Tag: 24jan2021_ls180~2099^2~275
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4d1b6da42fabcfd9987ae77056a4bab31780c6e1;p=litex.git

bus/csr: add configurable address_width (needed more than 32 modules with CSR)
---

diff --git a/migen/bus/csr.py b/migen/bus/csr.py
index 80ce0fcb..49dc5533 100644
--- a/migen/bus/csr.py
+++ b/migen/bus/csr.py
@@ -5,16 +5,16 @@ from migen.genlib.record import *
 from migen.genlib.misc import chooser
 
 _layout = [
-	("adr",		14,				DIR_M_TO_S),
-	("we",		1,				DIR_M_TO_S),
-	("dat_w",	"data_width",	DIR_M_TO_S),
-	("dat_r",	"data_width",	DIR_S_TO_M)
+	("adr",		"address_width",	DIR_M_TO_S),
+	("we",		1,					DIR_M_TO_S),
+	("dat_w",	"data_width",		DIR_M_TO_S),
+	("dat_r",	"data_width",		DIR_S_TO_M)
 ]
 
 class Interface(Record):
-	def __init__(self, data_width=8):
+	def __init__(self, data_width=8, address_width=14):
 		Record.__init__(self, set_layout_parameters(_layout,
-			data_width=data_width))
+			data_width=data_width, address_width=address_width))
 
 class Interconnect(Module):
 	def __init__(self, master, slaves):