From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Wed, 10 Jun 2020 15:25:20 +0000 (+0200)
Subject: Remove SDR/DDR/DDR2 modules (unsupported)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4d1f5a2b62702aeeea523dc57278da4d69ccbc4e;p=gram.git

Remove SDR/DDR/DDR2 modules (unsupported)
---

diff --git a/gram/modules.py b/gram/modules.py
index d3790f8..e481f33 100644
--- a/gram/modules.py
+++ b/gram/modules.py
@@ -321,243 +321,6 @@ class SDRAMModule:
 class SDRAMRegisteredModule(SDRAMModule):
     registered = True
 
-# SDR ----------------------------------------------------------------------------------------------
-
-
-class SDRModule(SDRAMModule):
-    memtype = "SDR"
-
-
-class SDRRegisteredModule(SDRAMRegisteredModule):
-    memtype = "SDR"
-
-
-class IS42S16160(SDRModule):
-    # geometry
-    nbanks = 4
-    nrows = 8192
-    ncols = 512
-    # timings
-    technology_timings = _TechnologyTimings(
-        tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
-    speedgrade_timings = {"default": _SpeedgradeTimings(
-        tRP=20, tRCD=20, tWR=20, tRFC=(None, 70), tFAW=None, tRAS=None)}
-
-
-class IS42S16320(SDRModule):
-    # geometry
-    nbanks = 4
-    nrows = 8192
-    ncols = 1024
-    # timings
-    technology_timings = _TechnologyTimings(
-        tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
-    speedgrade_timings = {"default": _SpeedgradeTimings(
-        tRP=20, tRCD=20, tWR=20, tRFC=(None, 70), tFAW=None, tRAS=None)}
-
-
-class MT48LC4M16(SDRModule):
-    # geometry
-    nbanks = 4
-    nrows = 4096
-    ncols = 256
-    # timings
-    technology_timings = _TechnologyTimings(
-        tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
-    speedgrade_timings = {"default": _SpeedgradeTimings(
-        tRP=15, tRCD=15, tWR=14, tRFC=(None, 66), tFAW=None, tRAS=None)}
-
-
-class MT48LC16M16(SDRModule):
-    # geometry
-    nbanks = 4
-    nrows = 8192
-    ncols = 512
-    # timings
-    technology_timings = _TechnologyTimings(
-        tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 15))
-    speedgrade_timings = {"default": _SpeedgradeTimings(
-        tRP=20, tRCD=20, tWR=15, tRFC=(None, 66), tFAW=None, tRAS=44)}
-
-
-class AS4C16M16(SDRModule):
-    # geometry
-    nbanks = 4
-    nrows = 8192
-    ncols = 512
-    # timings
-    technology_timings = _TechnologyTimings(
-        tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
-    speedgrade_timings = {"default": _SpeedgradeTimings(
-        tRP=18, tRCD=18, tWR=12, tRFC=(None, 60), tFAW=None, tRAS=None)}
-
-
-class AS4C32M16(SDRModule):
-    # geometry
-    nbanks = 4
-    nrows = 8192
-    ncols = 1024
-    # timings
-    technology_timings = _TechnologyTimings(
-        tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
-    speedgrade_timings = {"default": _SpeedgradeTimings(
-        tRP=18, tRCD=18, tWR=12, tRFC=(None, 60), tFAW=None, tRAS=None)}
-
-
-class AS4C32M8(SDRModule):
-    # geometry
-    nbanks = 4
-    nrows = 8192
-    ncols = 1024
-    # timings
-    technology_timings = _TechnologyTimings(
-        tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 15))
-    speedgrade_timings = {"default": _SpeedgradeTimings(
-        tRP=20, tRCD=20, tWR=15, tRFC=(None, 66), tFAW=None, tRAS=44)}
-
-
-class M12L64322A(SDRModule):
-    # geometry
-    nbanks = 4
-    nrows = 2048
-    ncols = 256
-    # timings
-    technology_timings = _TechnologyTimings(
-        tREFI=64e6/4096, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 10))
-    speedgrade_timings = {"default": _SpeedgradeTimings(
-        tRP=15, tRCD=15, tWR=15, tRFC=(None, 55), tFAW=None, tRAS=40)}
-
-
-class M12L16161A(SDRModule):
-    # geometry
-    nbanks = 2
-    nrows = 2048
-    ncols = 256
-    # timings
-    technology_timings = _TechnologyTimings(
-        tREFI=64e6/4096, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 10))
-    speedgrade_timings = {"default": _SpeedgradeTimings(
-        tRP=15, tRCD=15, tWR=15, tRFC=(None, 55), tFAW=None, tRAS=40)}
-
-# DDR ----------------------------------------------------------------------------------------------
-
-
-class DDRModule(SDRAMModule):
-    memtype = "DDR"
-
-
-class DDRRegisteredModule(SDRAMRegisteredModule):
-    memtype = "DDR"
-
-
-class MT46V32M16(SDRAMModule):
-    memtype = "DDR"
-    # geometry
-    nbanks = 4
-    nrows = 8192
-    ncols = 1024
-    # timings
-    technology_timings = _TechnologyTimings(
-        tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
-    speedgrade_timings = {"default": _SpeedgradeTimings(
-        tRP=15, tRCD=15, tWR=15, tRFC=(None, 70), tFAW=None, tRAS=None)}
-
-# LPDDR --------------------------------------------------------------------------------------------
-
-
-class LPDDRModule(SDRAMModule):
-    memtype = "LPDDR"
-
-
-class LPDDRRegisteredModule(SDRAMRegisteredModule):
-    memtype = "LPDDR"
-
-
-class MT46H32M16(LPDDRModule):
-    # geometry
-    nbanks = 4
-    nrows = 8192
-    ncols = 1024
-    # timings
-    technology_timings = _TechnologyTimings(
-        tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
-    speedgrade_timings = {"default": _SpeedgradeTimings(
-        tRP=15, tRCD=15, tWR=15, tRFC=(None, 72), tFAW=None, tRAS=None)}
-
-
-class MT46H32M32(LPDDRModule):
-    # geometry
-    nbanks = 4
-    nrows = 8192
-    ncols = 1024
-    # timings
-    technology_timings = _TechnologyTimings(
-        tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
-    speedgrade_timings = {"default": _SpeedgradeTimings(
-        tRP=15, tRCD=15, tWR=15, tRFC=(None, 72), tFAW=None, tRAS=None)}
-
-# DDR2 ---------------------------------------------------------------------------------------------
-
-
-class DDR2Module(SDRAMModule):
-    memtype = "DDR2"
-
-
-class DDR2RegisteredModule(SDRAMRegisteredModule):
-    memtype = "DDR2"
-
-
-class MT47H128M8(DDR2Module):
-    memtype = "DDR2"
-    # geometry
-    nbanks = 8
-    nrows = 16384
-    ncols = 1024
-    # timings
-    technology_timings = _TechnologyTimings(
-        tREFI=64e6/8192, tWTR=(None, 7.5), tCCD=(2, None), tRRD=None)
-    speedgrade_timings = {"default": _SpeedgradeTimings(
-        tRP=15, tRCD=15, tWR=15, tRFC=(None, 127.5), tFAW=None, tRAS=None)}
-
-
-class MT47H32M16(DDR2Module):
-    memtype = "DDR2"
-    # geometry
-    nbanks = 4
-    nrows = 8192
-    ncols = 1024
-    # timings
-    technology_timings = _TechnologyTimings(
-        tREFI=64e6/8192, tWTR=(None, 7.5), tCCD=(2, None), tRRD=None)
-    speedgrade_timings = {"default": _SpeedgradeTimings(
-        tRP=15, tRCD=15, tWR=15, tRFC=(None, 127.5), tFAW=None, tRAS=None)}
-
-
-class MT47H64M16(DDR2Module):
-    memtype = "DDR2"
-    # geometry
-    nbanks = 8
-    nrows = 8192
-    ncols = 1024
-    # timings
-    technology_timings = _TechnologyTimings(
-        tREFI=64e6/8192, tWTR=(None, 7.5), tCCD=(2, None), tRRD=None)
-    speedgrade_timings = {"default": _SpeedgradeTimings(
-        tRP=15, tRCD=15, tWR=15, tRFC=(None, 127.5), tFAW=None, tRAS=None)}
-
-
-class P3R1GE4JGF(DDR2Module):
-    memtype = "DDR2"
-    # geometry
-    nbanks = 8
-    nrows = 8192
-    ncols = 1024
-    # timings
-    technology_timings = _TechnologyTimings(
-        tREFI=64e6/8192, tWTR=(None, 7.5), tCCD=(2, None), tRRD=None)
-    speedgrade_timings = {"default": _SpeedgradeTimings(
-        tRP=12.5, tRCD=12.5, tWR=15, tRFC=(None, 127.5), tFAW=None, tRAS=None)}
-
 # DDR3 (Chips) -------------------------------------------------------------------------------------
 
 
@@ -897,61 +660,3 @@ class MT40A512M16(DDR4Module):
         "2400": _SpeedgradeTimings(tRP=13.32, tRCD=13.32, tWR=15, tRFC=trfc, tFAW=(20, 25), tRAS=32),
     }
     speedgrade_timings["default"] = speedgrade_timings["2400"]
-
-# DDR4 (SO-DIMM) -----------------------------------------------------------------------------------
-
-
-class KVR21SE15S84(DDR4Module):
-    # geometry
-    ngroupbanks = 4
-    ngroups = 4
-    nbanks = ngroups * ngroupbanks
-    nrows = 32768
-    ncols = 1024
-    # timings
-    trefi = {"1x": 64e6/8192,   "2x": (64e6/8192)/2, "4x": (64e6/8192)/4}
-    trfc = {"1x": (None, 350), "2x": (None, 260),   "4x": (None, 160)}
-    technology_timings = _TechnologyTimings(tREFI=trefi, tWTR=(
-        4, 7.5), tCCD=(4, None), tRRD=(4, 4.9), tZQCS=(128, 80))
-    speedgrade_timings = {
-        "2133": _SpeedgradeTimings(tRP=13.5, tRCD=13.5, tWR=15, tRFC=trfc, tFAW=(20, 25), tRAS=33),
-    }
-    speedgrade_timings["default"] = speedgrade_timings["2133"]
-
-
-class MTA4ATF51264HZ(DDR4Module):
-    # geometry
-    ngroupbanks = 4
-    ngroups = 2
-    nbanks = ngroups * ngroupbanks
-    nrows = 65536
-    ncols = 1024
-    # timings
-    trefi = {"1x": 64e6/8192,   "2x": (64e6/8192)/2, "4x": (64e6/8192)/4}
-    trfc = {"1x": (None, 350), "2x": (None, 260),   "4x": (None, 160)}
-    technology_timings = _TechnologyTimings(tREFI=trefi, tWTR=(
-        4, 7.5), tCCD=(4, None), tRRD=(4, 4.9), tZQCS=(128, 80))
-    speedgrade_timings = {
-        "2133": _SpeedgradeTimings(tRP=13.5, tRCD=13.5, tWR=15, tRFC=trfc, tFAW=(20, 25), tRAS=33),
-    }
-    speedgrade_timings["default"] = speedgrade_timings["2133"]
-
-# DDR4 (RDIMM) -------------------------------------------------------------------------------------
-
-
-class MTA18ASF2G72PZ(DDR4RegisteredModule):
-    # geometry
-    ngroupbanks = 4
-    ngroups = 4
-    nbanks = ngroups * ngroupbanks
-    nrows = 131072
-    ncols = 1024
-    # timings
-    trefi = {"1x": 64e6/8192,   "2x": (64e6/8192)/2, "4x": (64e6/8192)/4}
-    trfc = {"1x": (None, 350), "2x": (None, 260),   "4x": (None, 160)}
-    technology_timings = _TechnologyTimings(tREFI=trefi, tWTR=(
-        4, 7.5), tCCD=(4, None), tRRD=(4, 4.9), tZQCS=(128, 80))
-    speedgrade_timings = {
-        "2400": _SpeedgradeTimings(tRP=13.32, tRCD=13.32, tWR=15, tRFC=trfc, tFAW=(20, 25), tRAS=32),
-    }
-    speedgrade_timings["default"] = speedgrade_timings["2400"]