From: bugzilla-daemon <bugzilla-daemon@libre-riscv.org>
Date: Thu, 26 Mar 2020 21:41:16 +0000 (+0000)
Subject: [libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4d237dffa834e8dfa4b0e6ac54997b895c7a0c70;p=libre-riscv-dev.git

[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
---

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+Date: Thu, 26 Mar 2020 21:41:16 +0000
+X-Bugzilla-Reason: CC
+X-Bugzilla-Type: changed
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+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Specification
+X-Bugzilla-Version: unspecified
+X-Bugzilla-Keywords: 
+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: programmerjake@gmail.com
+X-Bugzilla-Status: CONFIRMED
+X-Bugzilla-Resolution: 
+X-Bugzilla-Priority: ---
+X-Bugzilla-Assigned-To: lkcl@lkcl.net
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+Message-ID: <bug-186-13-2212j6ICZa@http.bugs.libre-riscv.org/>
+In-Reply-To: <bug-186-13@http.bugs.libre-riscv.org/>
+References: <bug-186-13@http.bugs.libre-riscv.org/>
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+Auto-Submitted: auto-generated
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+Subject: [libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and
+ RISC-V
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