From: Luke Kenneth Casson Leighton Date: Thu, 26 Mar 2020 21:37:12 +0000 (+0000) Subject: Re: [libre-riscv-dev] cache SRAM organisation X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4d28f75764c7e8b27fcde29433b8c883f9cb6662;p=libre-riscv-dev.git Re: [libre-riscv-dev] cache SRAM organisation --- diff --git a/92/5c7a028146e90d23c4a944605615c8700c01b3 b/92/5c7a028146e90d23c4a944605615c8700c01b3 new file mode 100644 index 0000000..204f18f --- /dev/null +++ b/92/5c7a028146e90d23c4a944605615c8700c01b3 @@ -0,0 +1,110 @@ +Return-path: +Envelope-to: publicinbox@libre-riscv.org +Delivery-date: Thu, 26 Mar 2020 21:37:47 +0000 +Received: from localhost ([::1] helo=libre-riscv.org) + by libre-riscv.org with esmtp (Exim 4.89) + (envelope-from ) + id 1jHaCA-0005ab-81; Thu, 26 Mar 2020 21:37:46 +0000 +Received: from lkcl.net ([217.147.94.29]) + by libre-riscv.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) + (Exim 4.89) (envelope-from ) id 1jHaC8-0005aV-RE + for libre-riscv-dev@lists.libre-riscv.org; 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