From: bugzilla-daemon <bugzilla-daemon@libre-riscv.org>
Date: Fri, 3 Apr 2020 19:21:57 +0000 (+0000)
Subject: [libre-riscv-dev] [Bug 276] SR NAND Latch needed in nmigen
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4d31d47cfa8cbe8182290ca9f49f9d4864943ed1;p=libre-riscv-dev.git

[libre-riscv-dev] [Bug 276] SR NAND Latch needed in nmigen
---

diff --git a/61/71e7226acce0daa7879a412bbabf453f2f4021 b/61/71e7226acce0daa7879a412bbabf453f2f4021
new file mode 100644
index 0000000..3accd38
--- /dev/null
+++ b/61/71e7226acce0daa7879a412bbabf453f2f4021
@@ -0,0 +1,87 @@
+Return-path: <libre-riscv-dev-bounces@lists.libre-riscv.org>
+Envelope-to: publicinbox@libre-riscv.org
+Delivery-date: Fri, 03 Apr 2020 20:21:58 +0100
+Received: from localhost ([::1] helo=libre-riscv.org)
+	by libre-riscv.org with esmtp (Exim 4.89)
+	(envelope-from <libre-riscv-dev-bounces@lists.libre-riscv.org>)
+	id 1jKRt8-0004Fk-0x; Fri, 03 Apr 2020 20:21:58 +0100
+Received: from localhost ([127.0.0.1] helo=bugs.libre-riscv.org)
+ by libre-riscv.org with esmtp (Exim 4.89)
+ (envelope-from <bugzilla-daemon@libre-riscv.org>) id 1jKRt6-0004Fb-NV
+ for libre-riscv-dev@lists.libre-riscv.org; Fri, 03 Apr 2020 20:21:56 +0100
+From: bugzilla-daemon@libre-riscv.org
+To: libre-riscv-dev@lists.libre-riscv.org
+Date: Fri, 03 Apr 2020 19:21:57 +0000
+X-Bugzilla-Reason: CC
+X-Bugzilla-Type: changed
+X-Bugzilla-Watch-Reason: None
+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Source Code
+X-Bugzilla-Version: unspecified
+X-Bugzilla-Keywords: 
+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: lkcl@lkcl.net
+X-Bugzilla-Status: CONFIRMED
+X-Bugzilla-Resolution: 
+X-Bugzilla-Priority: ---
+X-Bugzilla-Assigned-To: lkcl@lkcl.net
+X-Bugzilla-Flags: 
+X-Bugzilla-Changed-Fields: 
+Message-ID: <bug-276-13-Nzca1UZVsS@http.bugs.libre-riscv.org/>
+In-Reply-To: <bug-276-13@http.bugs.libre-riscv.org/>
+References: <bug-276-13@http.bugs.libre-riscv.org/>
+X-Bugzilla-URL: http://bugs.libre-riscv.org/
+Auto-Submitted: auto-generated
+MIME-Version: 1.0
+Subject: [libre-riscv-dev] [Bug 276] SR NAND Latch needed in nmigen
+X-BeenThere: libre-riscv-dev@lists.libre-riscv.org
+X-Mailman-Version: 2.1.23
+Precedence: list
+List-Id: Libre-RISCV General Development
+ <libre-riscv-dev.lists.libre-riscv.org>
+List-Unsubscribe: <http://lists.libre-riscv.org/mailman/options/libre-riscv-dev>, 
+ <mailto:libre-riscv-dev-request@lists.libre-riscv.org?subject=unsubscribe>
+List-Archive: <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/>
+List-Post: <mailto:libre-riscv-dev@lists.libre-riscv.org>
+List-Help: <mailto:libre-riscv-dev-request@lists.libre-riscv.org?subject=help>
+List-Subscribe: <http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev>, 
+ <mailto:libre-riscv-dev-request@lists.libre-riscv.org?subject=subscribe>
+Reply-To: Libre-RISCV General Development
+ <libre-riscv-dev@lists.libre-riscv.org>
+Content-Type: text/plain; charset="utf-8"
+Content-Transfer-Encoding: base64
+Errors-To: libre-riscv-dev-bounces@lists.libre-riscv.org
+Sender: "libre-riscv-dev" <libre-riscv-dev-bounces@lists.libre-riscv.org>
+
+aHR0cDovL2J1Z3MubGlicmUtcmlzY3Yub3JnL3Nob3dfYnVnLmNnaT9pZD0yNzYKCi0tLSBDb21t
+ZW50ICMxMCBmcm9tIEx1a2UgS2VubmV0aCBDYXNzb24gTGVpZ2h0b24gPGxrY2xAbGtjbC5uZXQ+
+IC0tLQooSW4gcmVwbHkgdG8gU3RhZiBWZXJoYWVnZW4gZnJvbSBjb21tZW50ICM5KQo+IChJbiBy
+ZXBseSB0byBMdWtlIEtlbm5ldGggQ2Fzc29uIExlaWdodG9uIGZyb20gY29tbWVudCAjNSkKPiA+
+IChJbiByZXBseSB0byB3aGl0ZXF1YXJrIGZyb20gY29tbWVudCAjNCkKPiA+ID4gQWgsIHRoZXJl
+J3MgYW5vdGhlciBvcHRpb24gdGhhdCB5b3UgbWlnaHQgZmluZCBpbnRlcmVzdGluZy4gWW9zeXMg
+aGFzIGEKPiA+ID4gYCRzcmAgY29hcnNlIGNlbGwuIAo+ID4gCj4gPiB5ZXMuICB0aGlzIGkgX2Jl
+bGlldmVfIGlzIHdoYXQgU3RhZiBoYXMgaW1wbGVtZW50ZWQgZm9yIHVzLCBpbiB0aGUgbnN4bGli
+Cj4gPiBDZWxsIExpYnJhcnk6Cj4gPiBodHRwOi8vYnVncy5saWJyZS1yaXNjdi5vcmcvc2hvd19i
+dWcuY2dpP2lkPTE1NCNjMjEKPiAKPiBOb3QgcmVhbGx5LCBJIGltcGxlbWVudGVkIHRoZSBzdGFu
+ZGFyZCBjZWxscyBpbXBsZW1lbnRpbmcgdGhlIFNSIGxhdGNoZXMuIEEKPiB2YXJpYW50IHdpdGgg
+Tk9SIGdhdGVzIGFuZCBvbmUgd2l0aCBOQU5EIGdhdGVzIGFuZCB0d28gZHJpdmUgc3RyZW5ndGhz
+IG9mCj4gZWFjaC4KCmkgdGhpbmsgdGhhdCdzIHdoYXQgaSBtZWFudC4KaHR0cHM6Ly9naXRsYWIu
+bGlwNi5mci92bHNpLWVkYS9hbGxpYW5jZS1jaGVjay10b29sa2l0Ly0vbWVyZ2VfcmVxdWVzdHMv
+NC9kaWZmcwoKb2sgc28gdGhlc2UgYXJlIGNhbGxlZCBuc25ybGF0Y2ggYW5kIHNybGF0Y2gsIGFu
+ZCB0aGVyZSBhcmUgdGltZXMtMSBhbmQgdGltZXMtNAp2YXJpYW50cy4KCj4gWW9zeXMgYW5kIHN5
+bnRoZXNpcyB0aGUgbG9naWMgbmV0bGlzdCBjb21pbmcgZnJvbSBuTWlnZW4gbmVlZHMgdG8gbWFw
+cGVkIHRvCj4gdGhlIGNlbGxzIGluIHRoZSBsaWJyYXJ5IGlzIG9uIGEgaGlnaGVyIGxldmVsIHRo
+YW4gd2hhdCBJIGFtIGRvaW5nLgoKbXkgbWFpbiByZWFzb24gdG8gY3Jvc3MtcmVmIHdoYXQgeW91
+IGtpbmRseSB3cm90ZSBmb3Igb3VyIHVzZSB3YXMgdG8gaGlnaGxpZ2h0CnRoYXQgaXQgaGFkIGhh
+cHBlbmVkLgoKc28gbGV0IG1lIHRyeSB0byB1bmRlcnN0YW5kOgoKKiB5b3N5cyAkc3IgKGFuZCB2
+YXJpYW50cykgd2lsbCBuZWVkIHRvIG1hcCB0byB0aGVzZSBjZWxscyAobnNucmxhdGNoX3hOCiAg
+YW5kIHNybGF0Y2hfeE4pLgoKICB3aWxsIHRoaXMgbmVlZCBwYXRjaGVzIChvciBhIHBsdWdpbikg
+aW50byB5b3N5cz8KCiogbm1pZ2VuIHdpbGwgbmVlZCB0byBtYXAgdG8gJHNyCgogIGkgcHJlc3Vt
+ZSB0aGF0IGdpdmVuIHRoYXQgeW9zeXMgYWxyZWFkeSBoYXMgJHNyLCBvbmx5IG5taWdlbiB3aWxs
+IG5lZWQKICBhdWdtZW50aW5nIHRvIHByb2R1Y2UgJHNyPwoKLS0gCllvdSBhcmUgcmVjZWl2aW5n
+IHRoaXMgbWFpbCBiZWNhdXNlOgpZb3UgYXJlIG9uIHRoZSBDQyBsaXN0IGZvciB0aGUgYnVnLgpf
+X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpsaWJyZS1yaXNj
+di1kZXYgbWFpbGluZyBsaXN0CmxpYnJlLXJpc2N2LWRldkBsaXN0cy5saWJyZS1yaXNjdi5vcmcK
+aHR0cDovL2xpc3RzLmxpYnJlLXJpc2N2Lm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpYnJlLXJpc2N2
+LWRldgo=
+