From: Jean-François Nguyen <jf@lambdaconcept.com>
Date: Mon, 28 Jun 2021 13:47:15 +0000 (+0200)
Subject: test: _wishbone.py → utils/wishbone.py
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4d330f664b590bc6b539745d3d9068cd6b565814;p=lambdasoc.git

test: _wishbone.py → utils/wishbone.py
---

diff --git a/lambdasoc/test/_wishbone.py b/lambdasoc/test/_wishbone.py
deleted file mode 100644
index c7ab28c..0000000
--- a/lambdasoc/test/_wishbone.py
+++ /dev/null
@@ -1,34 +0,0 @@
-def wb_read(bus, addr, sel, timeout=32):
-    yield bus.cyc.eq(1)
-    yield bus.stb.eq(1)
-    yield bus.adr.eq(addr)
-    yield bus.sel.eq(sel)
-    yield
-    cycles = 0
-    while not (yield bus.ack):
-        yield
-        if cycles >= timeout:
-            raise RuntimeError("Wishbone transaction timed out")
-        cycles += 1
-    data = (yield bus.dat_r)
-    yield bus.cyc.eq(0)
-    yield bus.stb.eq(0)
-    return data
-
-def wb_write(bus, addr, data, sel, timeout=32):
-    yield bus.cyc.eq(1)
-    yield bus.stb.eq(1)
-    yield bus.adr.eq(addr)
-    yield bus.we.eq(1)
-    yield bus.sel.eq(sel)
-    yield bus.dat_w.eq(data)
-    yield
-    cycles = 0
-    while not (yield bus.ack):
-        yield
-        if cycles >= timeout:
-            raise RuntimeError("Wishbone transaction timed out")
-        cycles += 1
-    yield bus.cyc.eq(0)
-    yield bus.stb.eq(0)
-    yield bus.we.eq(0)
diff --git a/lambdasoc/test/test_periph_base.py b/lambdasoc/test/test_periph_base.py
index c3f59ff..abd4125 100644
--- a/lambdasoc/test/test_periph_base.py
+++ b/lambdasoc/test/test_periph_base.py
@@ -4,7 +4,7 @@ import unittest
 from nmigen import *
 from nmigen.back.pysim import *
 
-from ._wishbone import *
+from .utils.wishbone import *
 from ..periph.base import Peripheral, CSRBank, PeripheralBridge
 
 
diff --git a/lambdasoc/test/test_periph_serial.py b/lambdasoc/test/test_periph_serial.py
index e73c274..a4a59f0 100644
--- a/lambdasoc/test/test_periph_serial.py
+++ b/lambdasoc/test/test_periph_serial.py
@@ -4,7 +4,7 @@ from nmigen import *
 from nmigen.lib.io import pin_layout
 from nmigen.back.pysim import *
 
-from ._wishbone import *
+from .utils.wishbone import *
 from ..periph.serial import AsyncSerialPeripheral
 
 
diff --git a/lambdasoc/test/test_periph_sram.py b/lambdasoc/test/test_periph_sram.py
index 266de6d..103b3fb 100644
--- a/lambdasoc/test/test_periph_sram.py
+++ b/lambdasoc/test/test_periph_sram.py
@@ -8,7 +8,7 @@ from nmigen.back.pysim import *
 
 from nmigen_soc.wishbone import CycleType, BurstTypeExt
 
-from ._wishbone import *
+from .utils.wishbone import *
 from ..periph.sram import SRAMPeripheral
 
 
diff --git a/lambdasoc/test/test_periph_timer.py b/lambdasoc/test/test_periph_timer.py
index cdbb998..22540f7 100644
--- a/lambdasoc/test/test_periph_timer.py
+++ b/lambdasoc/test/test_periph_timer.py
@@ -5,7 +5,7 @@ import unittest
 from nmigen import *
 from nmigen.back.pysim import *
 
-from ._wishbone import *
+from .utils.wishbone import *
 from ..periph.timer import TimerPeripheral
 
 
diff --git a/lambdasoc/test/utils/__init__.py b/lambdasoc/test/utils/__init__.py
new file mode 100644
index 0000000..e69de29
diff --git a/lambdasoc/test/utils/wishbone.py b/lambdasoc/test/utils/wishbone.py
new file mode 100644
index 0000000..a2eef4a
--- /dev/null
+++ b/lambdasoc/test/utils/wishbone.py
@@ -0,0 +1,43 @@
+from nmigen import *
+
+from nmigen_soc import wishbone
+
+
+__all__ = ["wb_read", "wb_write"]
+
+
+def wb_read(bus, addr, sel, timeout=32):
+    yield bus.cyc.eq(1)
+    yield bus.stb.eq(1)
+    yield bus.adr.eq(addr)
+    yield bus.sel.eq(sel)
+    yield
+    cycles = 0
+    while not (yield bus.ack):
+        yield
+        if cycles >= timeout:
+            raise RuntimeError("Wishbone transaction timed out")
+        cycles += 1
+    data = (yield bus.dat_r)
+    yield bus.cyc.eq(0)
+    yield bus.stb.eq(0)
+    return data
+
+
+def wb_write(bus, addr, data, sel, timeout=32):
+    yield bus.cyc.eq(1)
+    yield bus.stb.eq(1)
+    yield bus.adr.eq(addr)
+    yield bus.we.eq(1)
+    yield bus.sel.eq(sel)
+    yield bus.dat_w.eq(data)
+    yield
+    cycles = 0
+    while not (yield bus.ack):
+        yield
+        if cycles >= timeout:
+            raise RuntimeError("Wishbone transaction timed out")
+        cycles += 1
+    yield bus.cyc.eq(0)
+    yield bus.stb.eq(0)
+    yield bus.we.eq(0)