From: lkcl <lkcl@web>
Date: Sat, 10 Sep 2022 00:51:04 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~540
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4d3fd5acc868a0c29832c821c4f564c2e07af56d;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 221b2881d..bb13521aa 100644
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -117,7 +117,7 @@ such large numbers of registers, even for Multi-Issue microarchitectures.
 * 24-bits are needed within the main SVP64 Prefix (equivalent to a 2-bit XO)
 * Another 24-bit (a second 2-bit XO) is needed for a planned future encoding,
   currently named "SVP64-Single" [^likeext001]
-* A third 24-bits (third 2-bit XO) is strongly recommended to be **reserved**
+* A third 24-bits (third 2-bit XO) is strongly recommended to be `RESERVED`
   such that future unforeseen capability is needed.
 * To hold all Vector Context, five SPRs are needed for userspace.
   If Supervisor and Hypervisor mode are to