From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Tue, 16 Jun 2020 14:20:32 +0000 (+0200)
Subject: Fix CSR attribute error
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4d44dfbac45ea39481ad531cfb1fddf7349d31b6;p=gram.git

Fix CSR attribute error
---

diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py
index cec4f6e..fc6c27f 100644
--- a/gram/phy/ecp5ddrphy.py
+++ b/gram/phy/ecp5ddrphy.py
@@ -250,7 +250,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
             rdpntr = Signal(3)
             wrpntr = Signal(3)
             rdly = Signal(7)
-            with m.If(self._dly_sel.storage[i]):
+            with m.If(self._dly_sel.w_data[i]):
                 with m.If(self._rdly_dq_rst.re):
                     m.d.sync += rdly.eq(0)
                 with m.Elif(self._rdly_dq_inc.re):
@@ -259,7 +259,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
             burstdet = Signal()
             dqs_read = Signal()
             dqs_bitslip = Signal(2)
-            with m.If(self._dly_sel.storage[i]):
+            with m.If(self._dly_sel.w_data[i]):
                 with m.If(self._rdly_dq_bitslip_rst.re):
                     m.d.sync += dqs_bitslip.eq(0)
                 with m.Elif(self._rdly_dq_bitslip.re):
@@ -279,7 +279,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
                                      i_ECLK=ClockSignal("sync2x"),
                                      i_RST=ResetSignal("sync2x"),
                                      i_DDRDEL=self.init.delay,
-                                     i_PAUSE=self.init.pause | self._dly_sel.storage[i],
+                                     i_PAUSE=self.init.pause | self._dly_sel.w_data[i],
 
                                      # Control
                                      # Assert LOADNs to use DDRDEL control