From: Harsha Jagasia Date: Tue, 12 Jul 2011 16:26:02 +0000 (+0000) Subject: AMD bdver2 Enablement X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4d652a1865628038acbfc0b9cab1ef7547d49d40;p=gcc.git AMD bdver2 Enablement 2011-07-12 Harsha Jagasia AMD bdver2 Enablement * config.gcc (i[34567]86-*-linux* | ...): Add bdver2. (case ${target}): Add bdver2. * config/i386/driver-i386.c (host_detect_local_cpu): Let -march=native recognize bdver2 processors. * config/i386/i386-c.c (ix86_target_macros_internal): Add bdver2 def_and_undef * config/i386/i386.c (struct processor_costs bdver2_cost): New bdver2 cost table. (m_BDVER2): New definition. (m_AMD_MULTIPLE): Includes m_BDVER2. (initial_ix86_tune_features): Add bdver2 tuning. (processor_target_table): Add bdver2 entry. (static const char *const cpu_names): Add bdver2 entry. (ix86_option_override_internal): Add bdver2 instruction sets. (ix86_issue_rate): Add bdver2. (ix86_adjust_cost): Add bdver2. (has_dispatch): Add bdver2. * config/i386/i386.h (TARGET_BDVER2): New definition. (enum target_cpu_default): Add TARGET_CPU_DEFAULT_bdver2. (enum processor_type): Add PROCESSOR_BDVER2. * config/i386/i386.md (define_attr "cpu"): Add bdver2. * config/i386/i386.opt ( mdispatch-scheduler): Add bdver2 to description. From-SVN: r176209 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ca55049e6b6..08da4b925ec 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,30 @@ +2011-07-12 Harsha Jagasia + + AMD bdver2 Enablement + * config.gcc (i[34567]86-*-linux* | ...): Add bdver2. + (case ${target}): Add bdver2. + * config/i386/driver-i386.c (host_detect_local_cpu): Let + -march=native recognize bdver2 processors. + * config/i386/i386-c.c (ix86_target_macros_internal): Add + bdver2 def_and_undef + * config/i386/i386.c (struct processor_costs bdver2_cost): New + bdver2 cost table. + (m_BDVER2): New definition. + (m_AMD_MULTIPLE): Includes m_BDVER2. + (initial_ix86_tune_features): Add bdver2 tuning. + (processor_target_table): Add bdver2 entry. + (static const char *const cpu_names): Add bdver2 entry. + (ix86_option_override_internal): Add bdver2 instruction sets. + (ix86_issue_rate): Add bdver2. + (ix86_adjust_cost): Add bdver2. + (has_dispatch): Add bdver2. + * config/i386/i386.h (TARGET_BDVER2): New definition. + (enum target_cpu_default): Add TARGET_CPU_DEFAULT_bdver2. + (enum processor_type): Add PROCESSOR_BDVER2. + * config/i386/i386.md (define_attr "cpu"): Add bdver2. + * config/i386/i386.opt ( mdispatch-scheduler): Add bdver2 to + description. + 2011-07-12 Richard Henderson PR target/49714 diff --git a/gcc/config.gcc b/gcc/config.gcc index aa27283519f..7343ef53032 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -1289,7 +1289,7 @@ i[34567]86-*-linux* | i[34567]86-*-kfreebsd*-gnu | i[34567]86-*-knetbsd*-gnu | i need_64bit_hwint=yes need_64bit_isa=yes case X"${with_cpu}" in - Xgeneric|Xatom|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver1|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3) + Xgeneric|Xatom|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver2|Xbdver1|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3) ;; X) if test x$with_cpu_64 = x; then @@ -1298,7 +1298,7 @@ i[34567]86-*-linux* | i[34567]86-*-kfreebsd*-gnu | i[34567]86-*-knetbsd*-gnu | i ;; *) echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2 - echo "generic atom core2 corei7 corei7-avx nocona x86-64 bdver1 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2 + echo "generic atom core2 corei7 corei7-avx nocona x86-64 bdver2 bdver1 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2 exit 1 ;; esac @@ -1414,7 +1414,7 @@ i[34567]86-*-solaris2* | x86_64-*-solaris2.1[0-9]*) need_64bit_hwint=yes need_64bit_isa=yes case X"${with_cpu}" in - Xgeneric|Xatom|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver1|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3) + Xgeneric|Xatom|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver2|Xbdver1|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3) ;; X) if test x$with_cpu_64 = x; then @@ -1423,7 +1423,7 @@ i[34567]86-*-solaris2* | x86_64-*-solaris2.1[0-9]*) ;; *) echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2 - echo "generic atom core2 corei7 corei7-avx nocona x86-64 bdver1 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2 + echo "generic atom core2 corei7 corei7-avx nocona x86-64 bdver2 bdver1 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2 exit 1 ;; esac @@ -1493,7 +1493,7 @@ i[34567]86-*-mingw* | x86_64-*-mingw*) if test x$enable_targets = xall; then tm_defines="${tm_defines} TARGET_BI_ARCH=1" case X"${with_cpu}" in - Xgeneric|Xatom|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver1|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3) + Xgeneric|Xatom|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver2|Xbdver1|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3) ;; X) if test x$with_cpu_64 = x; then @@ -1502,7 +1502,7 @@ i[34567]86-*-mingw* | x86_64-*-mingw*) ;; *) echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2 - echo "generic atom core2 corei7 Xcorei7-avx nocona x86-64 bdver1 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2 + echo "generic atom core2 corei7 Xcorei7-avx nocona x86-64 bdver2 bdver1 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2 exit 1 ;; esac @@ -2748,6 +2748,10 @@ case ${target} in ;; i686-*-* | i786-*-*) case ${target_noncanonical} in + bdver2-*) + arch=bdver2 + cpu=bdver2 + ;; bdver1-*) arch=bdver1 cpu=bdver1 @@ -2841,6 +2845,10 @@ case ${target} in ;; x86_64-*-*) case ${target_noncanonical} in + bdver2-*) + arch=bdver2 + cpu=bdver2 + ;; bdver1-*) arch=bdver1 cpu=bdver1 @@ -3276,8 +3284,9 @@ case "${target}" in ;; "" | x86-64 | generic | native \ | k8 | k8-sse3 | athlon64 | athlon64-sse3 | opteron \ - | opteron-sse3 | athlon-fx | bdver1 | btver1 | amdfam10 \ - | barcelona | nocona | core2 | corei7 | corei7-avx | atom) + | opteron-sse3 | athlon-fx | bdver2 | bdver1 | btver1 \ + | amdfam10 | barcelona | nocona | core2 | corei7 \ + | corei7-avx | atom) # OK ;; *) diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c index efd43729fb8..ecd8958df23 100644 --- a/gcc/config/i386/driver-i386.c +++ b/gcc/config/i386/driver-i386.c @@ -499,6 +499,8 @@ const char *host_detect_local_cpu (int argc, const char **argv) if (name == SIG_GEODE) processor = PROCESSOR_GEODE; + else if (has_bmi) + processor = PROCESSOR_BDVER2; else if (has_xop) processor = PROCESSOR_BDVER1; else if (has_sse4a && has_ssse3) @@ -664,6 +666,9 @@ const char *host_detect_local_cpu (int argc, const char **argv) case PROCESSOR_BDVER1: cpu = "bdver1"; break; + case PROCESSOR_BDVER2: + cpu = "bdver2"; + break; case PROCESSOR_BTVER1: cpu = "btver1"; break; diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c index 56765484364..5cbcfd51c68 100644 --- a/gcc/config/i386/i386-c.c +++ b/gcc/config/i386/i386-c.c @@ -110,6 +110,10 @@ ix86_target_macros_internal (int isa_flag, def_or_undef (parse_in, "__bdver1"); def_or_undef (parse_in, "__bdver1__"); break; + case PROCESSOR_BDVER2: + def_or_undef (parse_in, "__bdver2"); + def_or_undef (parse_in, "__bdver2__"); + break; case PROCESSOR_BTVER1: def_or_undef (parse_in, "__btver1"); def_or_undef (parse_in, "__btver1__"); @@ -198,6 +202,9 @@ ix86_target_macros_internal (int isa_flag, case PROCESSOR_BDVER1: def_or_undef (parse_in, "__tune_bdver1__"); break; + case PROCESSOR_BDVER2: + def_or_undef (parse_in, "__tune_bdver2__"); + break; case PROCESSOR_BTVER1: def_or_undef (parse_in, "__tune_btver1__"); break; diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 4ca95ab25a6..e75e1b1d35e 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -1338,6 +1338,93 @@ struct processor_costs bdver1_cost = { 1, /* cond_not_taken_branch_cost. */ }; +struct processor_costs bdver2_cost = { + COSTS_N_INSNS (1), /* cost of an add instruction */ + COSTS_N_INSNS (1), /* cost of a lea instruction */ + COSTS_N_INSNS (1), /* variable shift costs */ + COSTS_N_INSNS (1), /* constant shift costs */ + {COSTS_N_INSNS (4), /* cost of starting multiply for QI */ + COSTS_N_INSNS (4), /* HI */ + COSTS_N_INSNS (4), /* SI */ + COSTS_N_INSNS (6), /* DI */ + COSTS_N_INSNS (6)}, /* other */ + 0, /* cost of multiply per each bit set */ + {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */ + COSTS_N_INSNS (35), /* HI */ + COSTS_N_INSNS (51), /* SI */ + COSTS_N_INSNS (83), /* DI */ + COSTS_N_INSNS (83)}, /* other */ + COSTS_N_INSNS (1), /* cost of movsx */ + COSTS_N_INSNS (1), /* cost of movzx */ + 8, /* "large" insn */ + 9, /* MOVE_RATIO */ + 4, /* cost for loading QImode using movzbl */ + {5, 5, 4}, /* cost of loading integer registers + in QImode, HImode and SImode. + Relative to reg-reg move (2). */ + {4, 4, 4}, /* cost of storing integer registers */ + 2, /* cost of reg,reg fld/fst */ + {5, 5, 12}, /* cost of loading fp registers + in SFmode, DFmode and XFmode */ + {4, 4, 8}, /* cost of storing fp registers + in SFmode, DFmode and XFmode */ + 2, /* cost of moving MMX register */ + {4, 4}, /* cost of loading MMX registers + in SImode and DImode */ + {4, 4}, /* cost of storing MMX registers + in SImode and DImode */ + 2, /* cost of moving SSE register */ + {4, 4, 4}, /* cost of loading SSE registers + in SImode, DImode and TImode */ + {4, 4, 4}, /* cost of storing SSE registers + in SImode, DImode and TImode */ + 2, /* MMX or SSE register to integer */ + /* On K8: + MOVD reg64, xmmreg Double FSTORE 4 + MOVD reg32, xmmreg Double FSTORE 4 + On AMDFAM10: + MOVD reg64, xmmreg Double FADD 3 + 1/1 1/1 + MOVD reg32, xmmreg Double FADD 3 + 1/1 1/1 */ + 16, /* size of l1 cache. */ + 2048, /* size of l2 cache. */ + 64, /* size of prefetch block */ + /* New AMD processors never drop prefetches; if they cannot be performed + immediately, they are queued. We set number of simultaneous prefetches + to a large constant to reflect this (it probably is not a good idea not + to limit number of prefetches at all, as their execution also takes some + time). */ + 100, /* number of parallel prefetches */ + 2, /* Branch cost */ + COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */ + COSTS_N_INSNS (6), /* cost of FMUL instruction. */ + COSTS_N_INSNS (42), /* cost of FDIV instruction. */ + COSTS_N_INSNS (2), /* cost of FABS instruction. */ + COSTS_N_INSNS (2), /* cost of FCHS instruction. */ + COSTS_N_INSNS (52), /* cost of FSQRT instruction. */ + + /* BDVER2 has optimized REP instruction for medium sized blocks, but for + very small blocks it is better to use loop. For large blocks, libcall + can do nontemporary accesses and beat inline considerably. */ + {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}}, + {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}}, + {{libcall, {{8, loop}, {24, unrolled_loop}, + {2048, rep_prefix_4_byte}, {-1, libcall}}}, + {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}}, + 6, /* scalar_stmt_cost. */ + 4, /* scalar load_cost. */ + 4, /* scalar_store_cost. */ + 6, /* vec_stmt_cost. */ + 0, /* vec_to_scalar_cost. */ + 2, /* scalar_to_vec_cost. */ + 4, /* vec_align_load_cost. */ + 4, /* vec_unalign_load_cost. */ + 4, /* vec_store_cost. */ + 2, /* cond_taken_branch_cost. */ + 1, /* cond_not_taken_branch_cost. */ +}; + struct processor_costs btver1_cost = { COSTS_N_INSNS (1), /* cost of an add instruction */ COSTS_N_INSNS (2), /* cost of a lea instruction */ @@ -1813,8 +1900,10 @@ const struct processor_costs *ix86_cost = &pentium_cost; #define m_ATHLON_K8 (m_K8 | m_ATHLON) #define m_AMDFAM10 (1<