From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 7 Sep 2021 21:37:06 +0000 (+0100)
Subject: fun fixing of get_core_hdl_regs, "yield from"
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4d76cc90de0dc9d97cd6f00a175194bccdde62a1;p=soc.git

fun fixing of get_core_hdl_regs, "yield from"
---

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index 646acef4..9cbba6c6 100644
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -148,10 +148,9 @@ def setup_regs(pdecode2, core, test):
     print("oe:", oe, oe_ok)
 
 
-def get_core_hdl_regs(dut, sim, core, test, code):
+def get_core_hdl_regs(dut, sim, core, test, code, intregs):
     # int regs
     # TODO, split this out into "core-register-getter" function
-    intregs = []
     for i in range(32):
         if core.regs.int.unary:
             rval = yield core.regs.int.regs[i].reg
@@ -159,7 +158,6 @@ def get_core_hdl_regs(dut, sim, core, test, code):
             rval = yield core.regs.int.memory._array[i]
         intregs.append(rval)
     print("core int regs", list(map(hex, intregs)))
-    return intregs
 
 
 def get_sim_regs(dut, sim, core, test, code):
@@ -183,11 +181,11 @@ def compare_core_sim_regs(dut,regsim,regcore, code):
 def check_regs(dut, sim, core, test, code):
 
     # Get regs and compare
-    intregs = get_core_hdl_regs(dut, sim, core, test, code)
+    intregs = [] # temporary hack workaround for yield
+    yield from get_core_hdl_regs(dut, sim, core, test, code, intregs)
     simregs = get_sim_regs(dut, sim, core, test, code)
     compare_core_sim_regs(dut,simregs,intregs,code)
 
-
     # TODO: exactly the same thing as above, except with CRs
 
     # CRs