From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Mar 2020 15:22:12 +0000 (-0700)
Subject: Code review fixes
X-Git-Tag: working-ls180~707^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4d897975a8fe76191c39442eb7603723a2b84e1d;p=yosys.git

Code review fixes
---

diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc
index 0111c2309..8b9d9a04d 100644
--- a/passes/memory/memory_share.cc
+++ b/passes/memory/memory_share.cc
@@ -670,13 +670,13 @@ struct MemoryShareWorker
 
 	void operator()(RTLIL::Module* module)
 	{
+		std::map<std::string, std::pair<std::vector<RTLIL::Cell*>, std::vector<RTLIL::Cell*>>> memindex;
+
 		this->module = module;
 		sigmap.set(module);
 		sig_to_mux.clear();
 		conditions_logic_cache.clear();
 
-		std::map<std::string, std::pair<std::vector<RTLIL::Cell*>, std::vector<RTLIL::Cell*>>> memindex;
-
 		sigmap_xmux = sigmap;
 		for (auto cell : module->cells())
 		{
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index c13184025..68d6ea82b 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -31,7 +31,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 bool did_something;
 
-void replace_undriven(RTLIL::Module *module, const CellTypes& ct)
+void replace_undriven(RTLIL::Module *module, const CellTypes &ct)
 {
 	SigMap sigmap(module);
 	SigPool driven_signals;