From: Jeff Law <law@redhat.com>
Date: Fri, 6 Dec 1996 05:30:24 +0000 (+0000)
Subject:         * simops.c: Fix thinkos in last change to "inc dn".
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4d8ced6cb15a1a98e565b93a97963df5eb4eca87;p=binutils-gdb.git

    * simops.c: Fix thinkos in last change to "inc dn".
---

diff --git a/sim/mn10300/ChangeLog b/sim/mn10300/ChangeLog
index 673189174a9..a1e0301c602 100644
--- a/sim/mn10300/ChangeLog
+++ b/sim/mn10300/ChangeLog
@@ -1,3 +1,7 @@
+Thu Dec  5 22:26:31 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* simops.c: Fix thinkos in last change to "inc dn".
+
 Wed Dec  4 10:57:53 1996  Jeffrey A Law  (law@cygnus.com)
 
 	* simops.c: "add imm,sp" does not effect the condition codes.
diff --git a/sim/mn10300/simops.c b/sim/mn10300/simops.c
index c3ecc4ec9ed..cebd1843354 100644
--- a/sim/mn10300/simops.c
+++ b/sim/mn10300/simops.c
@@ -1424,16 +1424,18 @@ void OP_F270 ()
 void OP_40 ()
 {
   int z,n,c,v;
-  unsigned int value;
+  unsigned int value, imm, reg1;
 
-  value = State.regs[REG_D0 + ((insn & 0xc) >> 2)] + 1;
+  reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
+  imm = 1;
+  value = reg1 + imm;
   State.regs[REG_D0 + ((insn & 0xc) >> 2)] = value;
 
   z = (value == 0);
   n = (value & 0x80000000);
-  c = (reg1 < reg2);
-  v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
-       && (reg2 & 0x80000000) != (value & 0x80000000));
+  c = (reg1 < imm);
+  v = ((reg1 & 0x80000000) != (imm & 0x80000000)
+       && (reg1 & 0x80000000) != (value & 0x80000000));
 
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)