From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 7 May 2015 18:03:12 +0000 (+0200)
Subject: liteusb/phy/ft245: rename "ftdi" clock domain to "usb"
X-Git-Tag: 24jan2021_ls180~2255
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4d902b578cd8a1dd6a04488d061c2c8db56a5b75;p=litex.git

liteusb/phy/ft245: rename "ftdi" clock domain to "usb"
---

diff --git a/misoclib/com/liteusb/phy/ft245.py b/misoclib/com/liteusb/phy/ft245.py
index bed5f5d6..28809c27 100644
--- a/misoclib/com/liteusb/phy/ft245.py
+++ b/misoclib/com/liteusb/phy/ft245.py
@@ -35,14 +35,14 @@ class FT245PHYSynchronous(Module):
 
         # read fifo (FTDI --> SoC)
         read_fifo = RenameClockDomains(AsyncFIFO(phy_description(8), fifo_depth),
-            {"write": "ftdi", "read": "sys"})
+                                       {"write": "usb", "read": "sys"})
         read_buffer = RenameClockDomains(SyncFIFO(phy_description(8), 4),
-            {"sys": "ftdi"})
+                                         {"sys": "usb"})
         self.comb += read_buffer.source.connect(read_fifo.sink)
 
         # write fifo (SoC --> FTDI)
         write_fifo = RenameClockDomains(AsyncFIFO(phy_description(8), fifo_depth),
-            {"write": "sys", "read": "ftdi"})
+                                        {"write": "sys", "read": "usb"})
 
         self.submodules += read_fifo, read_buffer, write_fifo
 
@@ -70,7 +70,7 @@ class FT245PHYSynchronous(Module):
         data_w_accepted = Signal(reset=1)
 
         fsm = FSM(reset_state="READ")
-        self.submodules += RenameClockDomains(fsm, {"sys": "ftdi"})
+        self.submodules += RenameClockDomains(fsm, {"sys": "usb"})
 
         fsm.act("READ",
             read_time_en.eq(1),
@@ -107,7 +107,7 @@ class FT245PHYSynchronous(Module):
         pads.rd_n.reset = 1
         pads.wr_n.reset = 1
 
-        self.sync.ftdi += [
+        self.sync.usb += [
             If(fsm.ongoing("READ"),
                 data_oe.eq(0),