From: Nikos Nikoleris <nikos.nikoleris@arm.com>
Date: Wed, 20 Dec 2017 12:13:08 +0000 (+0000)
Subject: arch-arm: Fix printing of the data cache maintenance instructions
X-Git-Tag: v19.0.0.0~2315
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4d9811cc5fd36a972e340ad82b14ab0ccaeb5cfa;p=gem5.git

arch-arm: Fix printing of the data cache maintenance instructions

Change-Id: I2322c7bf65b38cb07a1ea2b5dc25dfc5a0496cf0
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7825
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
---

diff --git a/src/arch/arm/insts/mem64.cc b/src/arch/arm/insts/mem64.cc
index 0aee63f2c..fa8fdf0af 100644
--- a/src/arch/arm/insts/mem64.cc
+++ b/src/arch/arm/insts/mem64.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2013 ARM Limited
+ * Copyright (c) 2011-2013,2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -53,9 +53,8 @@ SysDC64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
-    ccprintf(ss, ", [");
+    ccprintf(ss, ", ");
     printIntReg(ss, base);
-    ccprintf(ss, "]");
     return ss.str();
 }
 
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index ba97eff09..9c7a051f5 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2013, 2017 ARM Limited
+ * Copyright (c) 2010, 2012-2013, 2017-2018 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
@@ -321,16 +321,6 @@ RegImmRegShiftOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
     return ss.str();
 }
 
-std::string
-MiscRegRegImmMemOp::generateDisassembly(Addr pc,
-                                        const SymbolTable *symtab) const
-{
-    std::stringstream ss;
-    printMnemonic(ss);
-    printIntReg(ss, op1);
-    return ss.str();
-}
-
 std::string
 UnknownOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh
index 72d1694c9..5c387a500 100644
--- a/src/arch/arm/insts/misc.hh
+++ b/src/arch/arm/insts/misc.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2013, 2017 ARM Limited
+ * Copyright (c) 2010, 2012-2013, 2017-2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -344,23 +344,6 @@ class RegImmRegShiftOp : public PredOp
     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 };
 
-class MiscRegRegImmMemOp : public PredOp
-{
-  protected:
-    MiscRegIndex dest;
-    IntRegIndex op1;
-    uint64_t imm;
-
-    MiscRegRegImmMemOp(const char *mnem, ExtMachInst _machInst,
-                       OpClass __opClass, MiscRegIndex _dest, IntRegIndex _op1,
-                       uint64_t _imm) :
-        PredOp(mnem, _machInst, __opClass),
-        dest(_dest), op1(_op1), imm(_imm)
-    {}
-
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-};
-
 class UnknownOp : public PredOp
 {
   protected:
diff --git a/src/arch/arm/isa/insts/data64.isa b/src/arch/arm/isa/insts/data64.isa
index 41e36d350..dd87bed62 100644
--- a/src/arch/arm/isa/insts/data64.isa
+++ b/src/arch/arm/isa/insts/data64.isa
@@ -417,7 +417,7 @@ let {{
 
    '''
 
-    msrDCZVAIop = InstObjParams("dczva", "Dczva", "SysDC64",
+    msrDCZVAIop = InstObjParams("dc zva", "Dczva", "SysDC64",
                 { "ea_code" : msrdczva_ea_code,
                   "memacc_code" : ";", "use_uops" : 0,
                   "op_wb" : ";", "fa_code" : ";"}, ['IsStore', 'IsMemRef']);
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 8745e86bc..cf3d0e00f 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2010-2013,2017 ARM Limited
+// Copyright (c) 2010-2013,2017-2018 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -1073,8 +1073,8 @@ let {{
                                             Request::DST_POC);
         EA = Op1;
     '''
-    McrDcimvacIop = InstObjParams("mcr dcimvac", "McrDcimvac",
-                                  "MiscRegRegImmMemOp",
+    McrDcimvacIop = InstObjParams("mcr", "McrDcimvac",
+                                  "MiscRegRegImmOp",
                                   {"memacc_code": McrDcCheckCode,
                                    "postacc_code": "",
                                    "ea_code": McrDcimvacCode,
@@ -1092,8 +1092,8 @@ let {{
                                             Request::DST_POC);
         EA = Op1;
     '''
-    McrDccmvacIop = InstObjParams("mcr dccmvac", "McrDccmvac",
-                                  "MiscRegRegImmMemOp",
+    McrDccmvacIop = InstObjParams("mcr", "McrDccmvac",
+                                  "MiscRegRegImmOp",
                                   {"memacc_code": McrDcCheckCode,
                                    "postacc_code": "",
                                    "ea_code": McrDccmvacCode,
@@ -1111,8 +1111,8 @@ let {{
                                             Request::DST_POU);
         EA = Op1;
     '''
-    McrDccmvauIop = InstObjParams("mcr dccmvau", "McrDccmvau",
-                                  "MiscRegRegImmMemOp",
+    McrDccmvauIop = InstObjParams("mcr", "McrDccmvau",
+                                  "MiscRegRegImmOp",
                                   {"memacc_code": McrDcCheckCode,
                                    "postacc_code": "",
                                    "ea_code": McrDccmvauCode,
@@ -1131,8 +1131,8 @@ let {{
                                             Request::DST_POC);
         EA = Op1;
     '''
-    McrDccimvacIop = InstObjParams("mcr dccimvac", "McrDccimvac",
-                                  "MiscRegRegImmMemOp",
+    McrDccimvacIop = InstObjParams("mcr", "McrDccimvac",
+                                  "MiscRegRegImmOp",
                                   {"memacc_code": McrDcCheckCode,
                                    "postacc_code": "",
                                    "ea_code": McrDccimvacCode,