From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 14 May 2021 19:54:29 +0000 (+0100)
Subject: add FRA ISACaller name decoding
X-Git-Tag: 0.0.3~40
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4da5a706f1462b5c2682203ecdfb8a17cd0aaeee;p=openpower-isa.git

add FRA ISACaller name decoding
---

diff --git a/openpower/isatables/minor_31.csv b/openpower/isatables/minor_31.csv
index 1b3acc49..88e1aed8 100644
--- a/openpower/isatables/minor_31.csv
+++ b/openpower/isatables/minor_31.csv
@@ -92,6 +92,7 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 0b1101110101,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is8B,0,0,cix,0,0,0,NONE,0,0,ldcix,X
 0b0000110101,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,1,ldux,X
 0b0000010101,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,ldx,X
+0b1000010111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,FRT,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,1,lfsx,X
 0b0001110100,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,0,1,0,0,NONE,0,1,lharx,X
 0b0101110111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,1,1,0,0,0,NONE,0,1,lhaux,X
 0b0101010111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,1,0,0,0,0,NONE,0,1,lhax,X
diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 10657d71..26e88d03 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -387,6 +387,20 @@ def get_pdecode_idx_in(dec2, name):
             return in2, in2_isvec
         if in3_sel == In3Sel.RS.value:
             return in3, in3_isvec
+    elif name == 'FRA':
+        if in1_sel == In1Sel.FRA.value:
+            return in1, in1_isvec
+    elif name == 'FRB':
+        if in2_sel == In2Sel.FRB.value:
+            return in2, in2_isvec
+    elif name == 'FRC':
+        if in3_sel == In3Sel.FRC.value:
+            return in3, in3_isvec
+    elif name == 'FRS':
+        if in1_sel == In1Sel.FRS.value:
+            return in1, in1_isvec
+        if in2_sel == In2Sel.FRS.value:
+            return in2, in2_isvec
     return None, False
 
 
@@ -429,6 +443,15 @@ def get_pdecode_idx_out(dec2, name):
                                       OutSel.RT_OR_ZERO.value, out, o_isvec)
         if out_sel == OutSel.RT.value:
             return out, o_isvec
+    elif name == 'FRA':
+        print ("get_pdecode_idx_out", out_sel, OutSel.FRA.value, out, o_isvec)
+        if out_sel == OutSel.FRA.value:
+            return out, o_isvec
+    elif name == 'FRT':
+        print ("get_pdecode_idx_out", out_sel, OutSel.FRT.value,
+                                      OutSel.FRT.value, out, o_isvec)
+        if out_sel == OutSel.FRT.value:
+            return out, o_isvec
     print ("get_pdecode_idx_out not found", name)
     return None, False
 
@@ -448,7 +471,7 @@ class ISACaller:
     def __init__(self, decoder2, regfile, initial_sprs=None, initial_cr=0,
                  initial_mem=None, initial_msr=0,
                  initial_svstate=0,
-                 initial_insns=None, 
+                 initial_insns=None,
                  fpregfile=None,
                  respect_pc=False,
                  disassembly=None,
diff --git a/src/openpower/decoder/isa/test_caller_fp.py b/src/openpower/decoder/isa/test_caller_fp.py
index 7468cc51..a28e1eef 100644
--- a/src/openpower/decoder/isa/test_caller_fp.py
+++ b/src/openpower/decoder/isa/test_caller_fp.py
@@ -35,7 +35,7 @@ class DecoderTestCase(FHDLTestCase):
 
         with Program(lst, bigendian=False) as program:
             sim = self.run_tst_program(program, initial_mem=initial_mem)
-            print(sim.fpr(1))
+            print("FPR 1", sim.fpr(1))
             self.assertEqual(sim.fpr(1), SelectableInt(0x4040266666666666, 64))
 
     def run_tst_program(self, prog, initial_regs=None,
@@ -43,7 +43,9 @@ class DecoderTestCase(FHDLTestCase):
         if initial_regs is None:
             initial_regs = [0] * 32
         simulator = run_tst(prog, initial_regs, mem=initial_mem)
+        print ("GPRs")
         simulator.gpr.dump()
+        print ("FPRs")
         simulator.fpr.dump()
         return simulator