From: lkcl <lkcl@web>
Date: Mon, 25 Jul 2022 10:25:43 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1036
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4dab20ca16babdc30767339db73c206b3c47d1b0;p=libreriscv.git

---

diff --git a/openpower/sv/executive_summary.mdwn b/openpower/sv/executive_summary.mdwn
index ee08e2854..985e13d24 100644
--- a/openpower/sv/executive_summary.mdwn
+++ b/openpower/sv/executive_summary.mdwn
@@ -32,6 +32,11 @@ further pressure on Major Opcode space which was never designed with
 Scalable Vectors in mind in the first place.  Contrast with RISC-V which was
 designed over a 7 year period with Cray-style Vectors right from the start.*
 
+Even with this amount of time spent, SVP64 exceeds the capability of RVV.
+RISC-V could have been significanyly enhanced if Simple V had been applied
+to it: this possibility was investigated very early but the decision was
+Made to go with Power ISA instead.
+Therefore it is crucial to note that
 Simple-V is **not RISC-V and is not RISC-V Vectors**.
 [NEC SX Aurora](https://sxauroratsubasa.sakura.ne.jp/documents/guide/pdfs/Aurora_ISA_guide.pdf),
 [RVV](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc),