From: lkcl Date: Sun, 13 Mar 2022 18:20:33 +0000 (+0000) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~3068 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4dc3adb81f538038154f3d6b98a07263be8d765f;p=libreriscv.git --- diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn index f3c6b220a..ea0c3916e 100644 --- a/openpower/sv/bitmanip.mdwn +++ b/openpower/sv/bitmanip.mdwn @@ -337,14 +337,20 @@ and a means to set regular 64 bit patterns in one the two LUT2s are applied left-half (when not swapping) and right-half (when swapping) so as to allow a wider -range of options +range of options. +* A value of `0b11001010` for the immediate provides +the functionality of a standard "grev". +* `0b11101110` provides gorc + grevlut should be arranged so as to produce the constants needed to put into bext (bitextract) so as in turn to -be able to emulate x86 pmovmask instructions - +be able to emulate x86 pmovmask instructions . +This only requires 2 instructions (grevlut, bext). +The following +settings provide the required mask constants: | RA | RB | imm | iv | result | | ------- | ------- | ---------- | -- | ---------- | @@ -355,7 +361,10 @@ be able to emulate x86 pmovmask instructions