From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 13 Jul 2015 09:03:33 +0000 (+0200)
Subject: misoclib/video/dvisampler: add fifo_depth parameter
X-Git-Tag: 24jan2021_ls180~2208
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4dca66b23d9be47006a8c7d7347ed6afff4c0983;p=litex.git

misoclib/video/dvisampler: add fifo_depth parameter
---

diff --git a/misoclib/video/dvisampler/__init__.py b/misoclib/video/dvisampler/__init__.py
index c376fb01..1f56af0f 100644
--- a/misoclib/video/dvisampler/__init__.py
+++ b/misoclib/video/dvisampler/__init__.py
@@ -13,7 +13,7 @@ from misoclib.video.dvisampler.dma import DMA
 
 
 class DVISampler(Module, AutoCSR):
-    def __init__(self, pads, lasmim, n_dma_slots=2):
+    def __init__(self, pads, lasmim, n_dma_slots=2, fifo_depth=512):
         self.submodules.edid = EDID(pads)
         self.submodules.clocking = Clocking(pads)
 
@@ -63,7 +63,7 @@ class DVISampler(Module, AutoCSR):
             self.resdetection.vsync.eq(self.syncpol.vsync)
         ]
 
-        self.submodules.frame = FrameExtraction(24*lasmim.dw//32)
+        self.submodules.frame = FrameExtraction(24*lasmim.dw//32, fifo_depth)
         self.comb += [
             self.frame.valid_i.eq(self.syncpol.valid_o),
             self.frame.de.eq(self.syncpol.de),
diff --git a/misoclib/video/dvisampler/analysis.py b/misoclib/video/dvisampler/analysis.py
index e3bfc39d..ccc7667d 100644
--- a/misoclib/video/dvisampler/analysis.py
+++ b/misoclib/video/dvisampler/analysis.py
@@ -109,7 +109,7 @@ class ResolutionDetection(Module, AutoCSR):
 
 
 class FrameExtraction(Module, AutoCSR):
-    def __init__(self, word_width):
+    def __init__(self, word_width, fifo_depth):
         # in pix clock domain
         self.valid_i = Signal()
         self.vsync = Signal()
@@ -155,7 +155,7 @@ class FrameExtraction(Module, AutoCSR):
         ]
 
         # FIFO
-        fifo = RenameClockDomains(AsyncFIFO(word_layout, 512),
+        fifo = RenameClockDomains(AsyncFIFO(word_layout, fifo_depth),
             {"write": "pix", "read": "sys"})
         self.submodules += fifo
         self.comb += [