From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 1 May 2019 10:58:44 +0000 (+0200)
Subject: soc/interconnect/axi/AXI2Wishbone: add buffer on axi command to be sure command is... 
X-Git-Tag: 24jan2021_ls180~1252
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4dccb8a9eb305d52d30e9c2e563d1b814a6585a5;p=litex.git

soc/interconnect/axi/AXI2Wishbone: add buffer on axi command to be sure command is accepted before response is sent
---

diff --git a/litex/soc/interconnect/axi.py b/litex/soc/interconnect/axi.py
index 75163cbc..324f2874 100644
--- a/litex/soc/interconnect/axi.py
+++ b/litex/soc/interconnect/axi.py
@@ -122,10 +122,12 @@ class AXI2Wishbone(Module):
         assert axi.data_width    == len(wishbone.dat_r)
         assert axi.address_width == len(wishbone.adr) + 2
 
+        ax_buffer = stream.Buffer(ax_description(axi.address_width, axi.id_width))
         ax_burst = stream.Endpoint(ax_description(axi.address_width, axi.id_width))
         ax_beat = stream.Endpoint(ax_description(axi.address_width, axi.id_width))
-        ax_burst2beat = AXIBurst2Beat(ax_burst, ax_beat)
-        self.submodules += ax_burst2beat
+        self.comb += ax_burst.connect(ax_buffer.sink)
+        ax_burst2beat = AXIBurst2Beat(ax_buffer.source, ax_beat)
+        self.submodules += ax_buffer, ax_burst2beat
 
         _data       = Signal(axi.data_width)
         _addr  = Signal(axi.address_width)