From: Marek Olšák <marek.olsak@amd.com>
Date: Tue, 1 Sep 2020 22:04:57 +0000 (-0400)
Subject: radeonsi: stop using TGSI_PROPERTY_TES_SPACING
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4dd2d9098ba154738d7b96db4acc512945c550e6;p=mesa.git

radeonsi: stop using TGSI_PROPERTY_TES_SPACING

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6624>
---

diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c b/src/gallium/drivers/radeonsi/si_shader_nir.c
index 629a97cdf35..f9fc6423277 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -457,11 +457,6 @@ void si_nir_scan_shader(const struct nir_shader *nir, struct si_shader_info *inf
    info->stage = nir->info.stage;
 
    if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
-      STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 == PIPE_TESS_SPACING_EQUAL);
-      STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 == PIPE_TESS_SPACING_FRACTIONAL_ODD);
-      STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN + 1) % 3 == PIPE_TESS_SPACING_FRACTIONAL_EVEN);
-
-      info->properties[TGSI_PROPERTY_TES_SPACING] = (nir->info.tess.spacing + 1) % 3;
       info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW] = !nir->info.tess.ccw;
 
       if (info->base.tess.primitive_mode == GL_ISOLINES)
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 12b3d83061b..bb9d16fa0ab 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -313,7 +313,7 @@ static void si_set_tesseval_regs(struct si_screen *sscreen, const struct si_shad
 {
    const struct si_shader_info *info = &tes->info;
    unsigned tes_prim_mode = info->base.tess.primitive_mode;
-   unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
+   unsigned tes_spacing = info->base.tess.spacing;
    bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
    bool tes_point_mode = info->base.tess.point_mode;
    unsigned type, partitioning, topology, distribution_mode;
@@ -334,13 +334,13 @@ static void si_set_tesseval_regs(struct si_screen *sscreen, const struct si_shad
    }
 
    switch (tes_spacing) {
-   case PIPE_TESS_SPACING_FRACTIONAL_ODD:
+   case TESS_SPACING_FRACTIONAL_ODD:
       partitioning = V_028B6C_PART_FRAC_ODD;
       break;
-   case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
+   case TESS_SPACING_FRACTIONAL_EVEN:
       partitioning = V_028B6C_PART_FRAC_EVEN;
       break;
-   case PIPE_TESS_SPACING_EQUAL:
+   case TESS_SPACING_EQUAL:
       partitioning = V_028B6C_PART_INTEGER;
       break;
    default:
@@ -400,7 +400,7 @@ static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen, struct si_sh
       unsigned vtx_reuse_depth = 30;
 
       if (sel->info.stage == MESA_SHADER_TESS_EVAL &&
-          sel->info.properties[TGSI_PROPERTY_TES_SPACING] == PIPE_TESS_SPACING_FRACTIONAL_ODD)
+          sel->info.base.tess.spacing == TESS_SPACING_FRACTIONAL_ODD)
          vtx_reuse_depth = 14;
 
       assert(pm4->shader);