From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 12 Dec 2021 20:44:26 +0000 (+0000)
Subject: bring MMU exception out where AllFunctionUnits (and then core)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4ddb53899da12ee466b4b1b2cbefd271e251f605;p=soc.git

bring MMU exception out where AllFunctionUnits (and then core)
can get at it
---

diff --git a/src/soc/fu/compunits/compunits.py b/src/soc/fu/compunits/compunits.py
index ee9f4981..4077451c 100644
--- a/src/soc/fu/compunits/compunits.py
+++ b/src/soc/fu/compunits/compunits.py
@@ -242,6 +242,7 @@ class MMUFSMFunctionUnit(FunctionUnitBaseSingle):
 
     def __init__(self, idx, parent_pspec):
         super().__init__(MMUPipeSpec, FSMMMUStage, idx, parent_pspec)
+        self.exc_o = self.alu.exc_o # get at MMU exception
 
 
 class DivPipeFunctionUnit(FunctionUnitBaseSingle):
diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py
index 3517dcf5..3f20d9ab 100644
--- a/src/soc/fu/mmu/fsm.py
+++ b/src/soc/fu/mmu/fsm.py
@@ -45,6 +45,7 @@ class FSMMMUStage(ControlBase):
         # set up p/n data
         self.p.i_data = MMUInputData(pspec)
         self.n.o_data = MMUOutputData(pspec)
+        self.exc_o = self.n.o_data.exception # AllFunctionUnits needs this
 
         self.mmu = MMU()