From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 27 Jun 2019 03:02:19 +0000 (-0700)
Subject: Add WE to ECP5 dist RAM's abc_scc_break too
X-Git-Tag: working-ls180~1237^2~24
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4de25a1949c14f4c343eae957b9402b5ddb574c9;p=yosys.git

Add WE to ECP5 dist RAM's abc_scc_break too
---

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 0239d1afe..b678a14da 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -106,7 +106,7 @@ module PFUMX (input ALUT, BLUT, C0, output Z);
 endmodule
 
 // ---------------------------------------
-(* abc_box_id=2, abc_scc_break="DI" *)
+(* abc_box_id=2, abc_scc_break="DI,WRE" *)
 module TRELLIS_DPR16X4 (
 	input [3:0] DI,
 	input [3:0] WAD,