From: Jacob Lifshay Date: Mon, 7 Aug 2023 23:04:00 +0000 (-0700) Subject: split out instructions from openpower/isa/fixedldstcache.mdwn X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4de82661ca6596cbdb55b7b1d7c4f01011b3990e;p=openpower-isa.git split out instructions from openpower/isa/fixedldstcache.mdwn --- diff --git a/openpower/isa/fixedldstcache.mdwn b/openpower/isa/fixedldstcache.mdwn index 8215ec14..0325e001 100644 --- a/openpower/isa/fixedldstcache.mdwn +++ b/openpower/isa/fixedldstcache.mdwn @@ -9,132 +9,18 @@ -# Load Byte and Zero Caching Inhibited Indexed +[[!inline pagenames="openpower/isa/fixedldstcache/lbzcix" raw="yes"]] -X-Form +[[!inline pagenames="openpower/isa/fixedldstcache/lhzcix" raw="yes"]] -* lbzcix RT,RA,RB +[[!inline pagenames="openpower/isa/fixedldstcache/lwzcix" raw="yes"]] -Pseudo-code: +[[!inline pagenames="openpower/isa/fixedldstcache/ldcix" raw="yes"]] - b <- (RA|0) - EA <- b + (RB) - RT <- [0] * 56 || MEM(EA, 1) +[[!inline pagenames="openpower/isa/fixedldstcache/stbcix" raw="yes"]] -Special Registers Altered: +[[!inline pagenames="openpower/isa/fixedldstcache/sthcix" raw="yes"]] - None +[[!inline pagenames="openpower/isa/fixedldstcache/stwcix" raw="yes"]] -# Load Halfword and Zero Caching Inhibited Indexed - -X-Form - -* lhzcix RT,RA,RB - -Pseudo-code: - - b <- (RA|0) - EA <- b + (RB) - RT <- [0] * 48 || MEM(EA, 2) - -Special Registers Altered: - - None - -# Load Word and Zero Caching Inhibited Indexed - -X-Form - -* lwzcix RT,RA,RB - -Pseudo-code: - - b <- (RA|0) - EA <- b + (RB) - RT <- [0] * 32 || MEM(EA, 4) - -Special Registers Altered: - - None - -# Load Doubleword Caching Inhibited Indexed - -X-Form - -* ldcix RT,RA,RB - -Pseudo-code: - - b <- (RA|0) - EA <- b + (RB) - RT <- MEM(EA, 8) - -Special Registers Altered: - - None - -# Store Byte Caching Inhibited Indexed - -X-Form - -* stbcix RS,RA,RB - -Pseudo-code: - - b <- (RA|0) - EA <- b + (RB) - MEM(EA, 1) <- (RS)[56:63] - -Special Registers Altered: - - None - -# Store Halfword Caching Inhibited Indexed - -X-Form - -* sthcix RS,RA,RB - -Pseudo-code: - - b <- (RA|0) - EA <- b + (RB) - MEM(EA, 2) <- (RS)[48:63] - -Special Registers Altered: - - None - -# Store Word Caching Inhibited Indexed - -X-Form - -* stwcix RS,RA,RB - -Pseudo-code: - - b <- (RA|0) - EA <- b + (RB) - MEM(EA, 4) <- (RS)[32:63] - -Special Registers Altered: - - None - -# Store Doubleword Caching Inhibited Indexed - -X-Form - -* stdcix RS,RA,RB - -Pseudo-code: - - b <- (RA|0) - EA <- b + (RB) - MEM(EA, 8) <- (RS) - -Special Registers Altered: - - None - - +[[!inline pagenames="openpower/isa/fixedldstcache/stdcix" raw="yes"]] diff --git a/openpower/isa/fixedldstcache/lbzcix.mdwn b/openpower/isa/fixedldstcache/lbzcix.mdwn new file mode 100644 index 00000000..67804b4d --- /dev/null +++ b/openpower/isa/fixedldstcache/lbzcix.mdwn @@ -0,0 +1,13 @@ +# Load Byte and Zero Caching Inhibited Indexed + +X-Form + +* lbzcix RT,RA,RB + +Pseudo-code: + +[[!inline pagenames="openpower/isa/fixedldstcache/lbzcix_code" raw="yes"]] + +Special Registers Altered: + + None diff --git a/openpower/isa/fixedldstcache/lbzcix_code.mdwn b/openpower/isa/fixedldstcache/lbzcix_code.mdwn new file mode 100644 index 00000000..5e111071 --- /dev/null +++ b/openpower/isa/fixedldstcache/lbzcix_code.mdwn @@ -0,0 +1,3 @@ + b <- (RA|0) + EA <- b + (RB) + RT <- [0] * 56 || MEM(EA, 1) diff --git a/openpower/isa/fixedldstcache/ldcix.mdwn b/openpower/isa/fixedldstcache/ldcix.mdwn new file mode 100644 index 00000000..1926881f --- /dev/null +++ b/openpower/isa/fixedldstcache/ldcix.mdwn @@ -0,0 +1,13 @@ +# Load Doubleword Caching Inhibited Indexed + +X-Form + +* ldcix RT,RA,RB + +Pseudo-code: + +[[!inline pagenames="openpower/isa/fixedldstcache/ldcix_code" raw="yes"]] + +Special Registers Altered: + + None diff --git a/openpower/isa/fixedldstcache/ldcix_code.mdwn b/openpower/isa/fixedldstcache/ldcix_code.mdwn new file mode 100644 index 00000000..08e30ab2 --- /dev/null +++ b/openpower/isa/fixedldstcache/ldcix_code.mdwn @@ -0,0 +1,3 @@ + b <- (RA|0) + EA <- b + (RB) + RT <- MEM(EA, 8) diff --git a/openpower/isa/fixedldstcache/lhzcix.mdwn b/openpower/isa/fixedldstcache/lhzcix.mdwn new file mode 100644 index 00000000..7036a9d2 --- /dev/null +++ b/openpower/isa/fixedldstcache/lhzcix.mdwn @@ -0,0 +1,13 @@ +# Load Halfword and Zero Caching Inhibited Indexed + +X-Form + +* lhzcix RT,RA,RB + +Pseudo-code: + +[[!inline pagenames="openpower/isa/fixedldstcache/lhzcix_code" raw="yes"]] + +Special Registers Altered: + + None diff --git a/openpower/isa/fixedldstcache/lhzcix_code.mdwn b/openpower/isa/fixedldstcache/lhzcix_code.mdwn new file mode 100644 index 00000000..2b67300f --- /dev/null +++ b/openpower/isa/fixedldstcache/lhzcix_code.mdwn @@ -0,0 +1,3 @@ + b <- (RA|0) + EA <- b + (RB) + RT <- [0] * 48 || MEM(EA, 2) diff --git a/openpower/isa/fixedldstcache/lwzcix.mdwn b/openpower/isa/fixedldstcache/lwzcix.mdwn new file mode 100644 index 00000000..ec70aed6 --- /dev/null +++ b/openpower/isa/fixedldstcache/lwzcix.mdwn @@ -0,0 +1,13 @@ +# Load Word and Zero Caching Inhibited Indexed + +X-Form + +* lwzcix RT,RA,RB + +Pseudo-code: + +[[!inline pagenames="openpower/isa/fixedldstcache/lwzcix_code" raw="yes"]] + +Special Registers Altered: + + None diff --git a/openpower/isa/fixedldstcache/lwzcix_code.mdwn b/openpower/isa/fixedldstcache/lwzcix_code.mdwn new file mode 100644 index 00000000..d52786a4 --- /dev/null +++ b/openpower/isa/fixedldstcache/lwzcix_code.mdwn @@ -0,0 +1,3 @@ + b <- (RA|0) + EA <- b + (RB) + RT <- [0] * 32 || MEM(EA, 4) diff --git a/openpower/isa/fixedldstcache/stbcix.mdwn b/openpower/isa/fixedldstcache/stbcix.mdwn new file mode 100644 index 00000000..740e9a32 --- /dev/null +++ b/openpower/isa/fixedldstcache/stbcix.mdwn @@ -0,0 +1,13 @@ +# Store Byte Caching Inhibited Indexed + +X-Form + +* stbcix RS,RA,RB + +Pseudo-code: + +[[!inline pagenames="openpower/isa/fixedldstcache/stbcix_code" raw="yes"]] + +Special Registers Altered: + + None diff --git a/openpower/isa/fixedldstcache/stbcix_code.mdwn b/openpower/isa/fixedldstcache/stbcix_code.mdwn new file mode 100644 index 00000000..7b35d90a --- /dev/null +++ b/openpower/isa/fixedldstcache/stbcix_code.mdwn @@ -0,0 +1,3 @@ + b <- (RA|0) + EA <- b + (RB) + MEM(EA, 1) <- (RS)[56:63] diff --git a/openpower/isa/fixedldstcache/stdcix.mdwn b/openpower/isa/fixedldstcache/stdcix.mdwn new file mode 100644 index 00000000..aae8abd3 --- /dev/null +++ b/openpower/isa/fixedldstcache/stdcix.mdwn @@ -0,0 +1,15 @@ +# Store Doubleword Caching Inhibited Indexed + +X-Form + +* stdcix RS,RA,RB + +Pseudo-code: + +[[!inline pagenames="openpower/isa/fixedldstcache/stdcix_code" raw="yes"]] + +Special Registers Altered: + + None + + diff --git a/openpower/isa/fixedldstcache/stdcix_code.mdwn b/openpower/isa/fixedldstcache/stdcix_code.mdwn new file mode 100644 index 00000000..444bfe19 --- /dev/null +++ b/openpower/isa/fixedldstcache/stdcix_code.mdwn @@ -0,0 +1,3 @@ + b <- (RA|0) + EA <- b + (RB) + MEM(EA, 8) <- (RS) diff --git a/openpower/isa/fixedldstcache/sthcix.mdwn b/openpower/isa/fixedldstcache/sthcix.mdwn new file mode 100644 index 00000000..c9e8fd54 --- /dev/null +++ b/openpower/isa/fixedldstcache/sthcix.mdwn @@ -0,0 +1,13 @@ +# Store Halfword Caching Inhibited Indexed + +X-Form + +* sthcix RS,RA,RB + +Pseudo-code: + +[[!inline pagenames="openpower/isa/fixedldstcache/sthcix_code" raw="yes"]] + +Special Registers Altered: + + None diff --git a/openpower/isa/fixedldstcache/sthcix_code.mdwn b/openpower/isa/fixedldstcache/sthcix_code.mdwn new file mode 100644 index 00000000..2970b950 --- /dev/null +++ b/openpower/isa/fixedldstcache/sthcix_code.mdwn @@ -0,0 +1,3 @@ + b <- (RA|0) + EA <- b + (RB) + MEM(EA, 2) <- (RS)[48:63] diff --git a/openpower/isa/fixedldstcache/stwcix.mdwn b/openpower/isa/fixedldstcache/stwcix.mdwn new file mode 100644 index 00000000..cc14582d --- /dev/null +++ b/openpower/isa/fixedldstcache/stwcix.mdwn @@ -0,0 +1,13 @@ +# Store Word Caching Inhibited Indexed + +X-Form + +* stwcix RS,RA,RB + +Pseudo-code: + +[[!inline pagenames="openpower/isa/fixedldstcache/stwcix_code" raw="yes"]] + +Special Registers Altered: + + None diff --git a/openpower/isa/fixedldstcache/stwcix_code.mdwn b/openpower/isa/fixedldstcache/stwcix_code.mdwn new file mode 100644 index 00000000..dbe72186 --- /dev/null +++ b/openpower/isa/fixedldstcache/stwcix_code.mdwn @@ -0,0 +1,3 @@ + b <- (RA|0) + EA <- b + (RB) + MEM(EA, 4) <- (RS)[32:63]