From: Luke Kenneth Casson Leighton Date: Sun, 14 Oct 2018 04:46:37 +0000 (+0100) Subject: replace ^ operator with rv_xor X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4de8e9fa8d35cc2d42a3a3d120862661b135732e;p=riscv-isa-sim.git replace ^ operator with rv_xor --- diff --git a/riscv/insns/xor.h b/riscv/insns/xor.h index 771efa7..90cbd6a 100644 --- a/riscv/insns/xor.h +++ b/riscv/insns/xor.h @@ -1 +1 @@ -WRITE_RD(RS1 ^ RS2); +WRITE_RD(rv_xor(RS1, RS2)); diff --git a/riscv/insns/xori.h b/riscv/insns/xori.h index 33ce630..e3b91cd 100644 --- a/riscv/insns/xori.h +++ b/riscv/insns/xori.h @@ -1 +1 @@ -WRITE_RD(insn.i_imm() ^ RS1); +WRITE_RD(rv_xor(insn.i_imm(), RS1)); diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc index 475f86e..1b8e4f2 100644 --- a/riscv/sv_insn_redirect.cc +++ b/riscv/sv_insn_redirect.cc @@ -252,3 +252,8 @@ reg_t sv_proc_t::rv_or(reg_t lhs, reg_t rhs) return lhs | rhs; } +reg_t sv_proc_t::rv_xor(reg_t lhs, reg_t rhs) +{ + return lhs ^ rhs; +} + diff --git a/riscv/sv_insn_redirect.h b/riscv/sv_insn_redirect.h index 3f133be..af28646 100644 --- a/riscv/sv_insn_redirect.h +++ b/riscv/sv_insn_redirect.h @@ -101,6 +101,7 @@ public: reg_t rv_mul(reg_t lhs, reg_t rhs); reg_t rv_and(reg_t lhs, reg_t rhs); reg_t rv_or(reg_t lhs, reg_t rhs); + reg_t rv_xor(reg_t lhs, reg_t rhs); #include "sv_insn_decl.h" };