From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 30 Jan 2014 13:52:46 +0000 (+0100)
Subject: Bugfix in name resolution with generate blocks
X-Git-Tag: yosys-0.2.0~131
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4df7e03ec9eafb01e2237f307075ad8dd7b1da5a;p=yosys.git

Bugfix in name resolution with generate blocks
---

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index bd5da14e3..5a2d1ae6c 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1478,7 +1478,7 @@ void AstNode::expand_genblock(std::string index_var, std::string prefix, std::ma
 
 	for (size_t i = 0; i < children.size(); i++) {
 		AstNode *child = children[i];
-		if (child->type != AST_FUNCTION && child->type != AST_TASK)
+		if (child->type != AST_FUNCTION && child->type != AST_TASK && child->type != AST_PREFIX)
 			child->expand_genblock(index_var, prefix, name_map);
 	}
 
diff --git a/tests/simple/carryadd.v b/tests/simple/carryadd.v
new file mode 100644
index 000000000..4f777f790
--- /dev/null
+++ b/tests/simple/carryadd.v
@@ -0,0 +1,24 @@
+module carryadd(a, b, y);
+
+parameter WIDTH = 8;
+
+input [WIDTH-1:0] a, b;
+output [WIDTH-1:0] y;
+
+genvar i;
+generate
+	for (i = 0; i < WIDTH; i = i+1) begin:STAGE
+		wire IN1 = a[i], IN2 = b[i];
+		wire C, Y;
+		if (i == 0)
+			assign C = IN1 & IN2, Y = IN1 ^ IN2;
+		else
+			assign C = (IN1 & IN2) | ((IN1 | IN2) & STAGE[i-1].C),
+			       Y = IN1 ^ IN2 ^ STAGE[i-1].C;
+		assign y[i] = Y;
+	end
+endgenerate
+
+// assert property (y == a + b);
+
+endmodule