From: Alexandre Oliva <aoliva@redhat.com>
Date: Sat, 16 Mar 2002 23:58:35 +0000 (+0000)
Subject: mips.h (ISA_HAS_COND_TRAP): Not available on MIPS16.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4dffef52e8c67e18f6ad0251d133a002c4645dc4;p=gcc.git

mips.h (ISA_HAS_COND_TRAP): Not available on MIPS16.

* config/mips/mips.h (ISA_HAS_COND_TRAP): Not available on MIPS16.
* config/mips/mips.md (trap) [TARGET_MIPS16]: Emit `break 0'.

From-SVN: r50898
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4ff4a5c994f..cf1b7bd0f85 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,8 @@
 2002-03-16  Alexandre Oliva  <aoliva@redhat.com>
 
+	* config/mips/mips.h (ISA_HAS_COND_TRAP): Not available on MIPS16.
+	* config/mips/mips.md (trap) [TARGET_MIPS16]: Emit `break 0'.
+
 	* config/mips/mips.md (addsi3, adddi3): Use scratch register to
 	add register to non-constant into sp.
 
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index ded10123c19..644592d5533 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -660,7 +660,7 @@ extern void		sbss_section PARAMS ((void));
 				)
 
 /* ISA has conditional trap instructions.  */
-#define ISA_HAS_COND_TRAP	(mips_isa >= 2)
+#define ISA_HAS_COND_TRAP	(mips_isa >= 2 && ! TARGET_MIPS16)
 
 /* ISA has multiply-accumulate instructions, madd and msub.  */
 #define ISA_HAS_MADD_MSUB       (mips_isa == 32                         \
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 91df86cc052..b9490f045e0 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -546,6 +546,8 @@
 {
   if (ISA_HAS_COND_TRAP)
     return \"teq\\t$0,$0\";
+  else if (TARGET_MIPS16)
+    return \"break 0\";
   else
     return \"break\";
 }")