From: Xan <Xan@web>
Date: Wed, 25 Apr 2018 06:04:17 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~5537
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4e1622aaa01cb5b7e48b34b7588be2de4c0b1135;p=libreriscv.git

---

diff --git a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
index efb31d95d..521b4ae2a 100644
--- a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
+++ b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
@@ -111,7 +111,7 @@ Andes SIMD Packed ISA omits 8 bit shifts, but these can be encoded in Harmonised
 | UMIN16 rt, ra, rb   | Unsigned minimum         | VMIN (r24 <= rt,ra,rb <= r29), mm=00|
 | SMAX16 rt, ra, rb   | Signed maximum           | VMAX (r16 <= rt,ra,rb <= r23), mm=00|
 | UMAX16 rt, ra, rb   | Unsigned maximum         | VMAX (r24 <= rt,ra,rb <= r29), mm=00|
-| KABS16 rt, ra, rb   | Saturated absolute value | VSGNX (r16 <= rt <= r29, r16 <= ra,rb <= r23, mm=01 |
+| KABS16 rt, ra, rb   | Saturated absolute value | VSGNX (r16 <= rt <= r29, r16 <= ra,rb <= r23, mm=01) |
 
 ## 8-bit Miscellaneous instructions
 
@@ -121,4 +121,4 @@ Andes SIMD Packed ISA omits 8 bit shifts, but these can be encoded in Harmonised
 | UMIN8 rt, ra, rb   | Unsigned minimum         | VMIN (r8 <= rt,ra,rb <= r15), mm=00|
 | SMAX8 rt, ra, rb   | Signed maximum           | VMAX (r2 <= rt,ra,rb <= r7), mm=00|
 | UMAX8 rt, ra, rb   | Unsigned maximum         | VMAX (r8 <= rt,ra,rb <= r15), mm=00|
-| KABS8 rt, ra, rb   | Saturated absolute value | VSGNX (r2 <= rt <= r15, r2 <= ra,rb <= r8, mm=01 |
+| KABS8 rt, ra, rb   | Saturated absolute value | VSGNX (r2 <= rt <= r15, r2 <= ra,rb <= r8, mm=01) |