From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 13 May 2019 19:03:23 +0000 (+0100)
Subject: rename intermediate signals to wr_wait/rd_wait
X-Git-Tag: div_pipeline~2055
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4e1c12403ea6e9ff79ca9a6d6299ec8a8eb66bd8;p=soc.git

rename intermediate signals to wr_wait/rd_wait
---

diff --git a/src/scoreboard/fu_dep_cell.py b/src/scoreboard/fu_dep_cell.py
index 9f4bceb4..dc5daf39 100644
--- a/src/scoreboard/fu_dep_cell.py
+++ b/src/scoreboard/fu_dep_cell.py
@@ -16,16 +16,16 @@ class FUDependenceCell(Elaboratable):
         self.go_wr_i = Signal(reset_less=True) # Go Write in (left)
         self.go_rd_i = Signal(reset_less=True)  # Go Read in (left)
 
-        # outputs (latched rd/wr pend)
-        self.rd_pend_o = Signal(reset_less=True)   # read pending out (right)
-        self.wr_pend_o = Signal(reset_less=True)   # write pending out (right)
+        # outputs (latched rd/wr wait)
+        self.rd_wait_o = Signal(reset_less=True)   # read waiting out (right)
+        self.wr_wait_o = Signal(reset_less=True)   # write waiting out (right)
 
     def elaborate(self, platform):
         m = Module()
         m.submodules.rd_l = rd_l = SRLatch() # clock-sync'd
         m.submodules.wr_l = wr_l = SRLatch() # clock-sync'd
 
-        # write latch: reset on go_wr HI, set on write pending and issue
+        # write latch: reset on go_wr HI, set on write waiting and issue
         m.d.comb += wr_l.s.eq(self.issue_i & self.wr_pend_i)
         m.d.comb += wr_l.r.eq(self.go_wr_i)
 
@@ -34,8 +34,8 @@ class FUDependenceCell(Elaboratable):
         m.d.comb += rd_l.r.eq(self.go_rd_i)
 
         # Read/Write Pending Latches (read out horizontally)
-        m.d.comb += self.wr_pend_o.eq(wr_l.q)
-        m.d.comb += self.rd_pend_o.eq(rd_l.q)
+        m.d.comb += self.wr_wait_o.eq(wr_l.q)
+        m.d.comb += self.rd_wait_o.eq(rd_l.q)
 
         return m
 
@@ -45,8 +45,8 @@ class FUDependenceCell(Elaboratable):
         yield self.issue_i
         yield self.go_wr_i
         yield self.go_rd_i
-        yield self.rd_pend_o
-        yield self.wr_pend_o
+        yield self.rd_wait_o
+        yield self.wr_wait_o
                 
     def ports(self):
         return list(self)
diff --git a/src/scoreboard/fu_fu_matrix.py b/src/scoreboard/fu_fu_matrix.py
index 5ee7d702..965503a9 100644
--- a/src/scoreboard/fu_fu_matrix.py
+++ b/src/scoreboard/fu_fu_matrix.py
@@ -69,16 +69,16 @@ class FUFUDepMatrix(Elaboratable):
         # ---
         for x in range(self.n_fu_col):
             fu = fur[x]
-            rd_pend_o = []
-            wr_pend_o = []
+            rd_wait_o = []
+            wr_wait_o = []
             for y in range(self.n_fu_row):
                 dc = dm[x][y]
                 # accumulate cell outputs rd/wr-pending
-                rd_pend_o.append(dc.rd_pend_o)
-                wr_pend_o.append(dc.wr_pend_o)
+                rd_wait_o.append(dc.rd_wait_o)
+                wr_wait_o.append(dc.wr_wait_o)
             # connect cell reg-select outputs to Reg Vector In
-            m.d.comb += [fu.rd_pend_i.eq(Cat(*rd_pend_o)),
-                         fu.wr_pend_i.eq(Cat(*wr_pend_o)),
+            m.d.comb += [fu.rd_pend_i.eq(Cat(*rd_wait_o)),
+                         fu.wr_pend_i.eq(Cat(*wr_wait_o)),
                         ]
         # ---
         # connect Dependency Matrix dest/src1/src2/issue to module d/s/s/i