From: lkcl <lkcl@web>
Date: Thu, 22 Sep 2022 16:48:08 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~327
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4e207ec2e40f125b278b7f1f99821210beda1a06;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index fc27c620c..57e79a1d9 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -663,7 +663,6 @@ Condition Register Field (as opposed to the notation `CR[bit]`
 which accesses one bit of the 32 bit Power ISA v3.0B
 Condition Register).
 
-
 `CR{n}` refers to `CR0` when `n=0` and consequently, for CR0-7, is defined, in v3.0B pseudocode, as:
 
      CR{7-n} = CR[32+n*4:35+n*4]
@@ -689,9 +688,9 @@ analysis and research) to be as follows:
     # finally get the bit from the CR.
     CR_bit = (CR_reg & (1<<bit_index)) != 0
 
-When it comes to applying SV, it is the *CR Field* number `CR\_reg`
+When it comes to applying SV, it is the *CR Field* number `CR_reg`
 to which SV EXTRA2/3
-applies, **not** the `CR\_bit` portion (bits 3-4):
+applies, **not** the `CR_bit` portion (bits 3-4):
 
     if extra3_mode:
         spec = EXTRA3