From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 22 Jan 2015 20:23:14 +0000 (+0100)
Subject: fix build with upstream Migen/MiSoC
X-Git-Tag: 24jan2021_ls180~2572^2~21
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4e3190120e5a2ddf7af5f407978e177ba97935e1;p=litex.git

fix build with upstream Migen/MiSoC
---

diff --git a/make.py b/make.py
index bcd1a17a..8d5a4439 100644
--- a/make.py
+++ b/make.py
@@ -7,6 +7,7 @@ from migen.util.misc import autotype
 from migen.fhdl import verilog, edif
 from migen.fhdl.structure import _Fragment
 from mibuild import tools
+from mibuild.xilinx_common import *
 
 from misoclib.gensoc import cpuif
 
@@ -136,7 +137,12 @@ BIST: {}
 		if not isinstance(soc, _Fragment):
 			soc = soc.get_fragment()
 		platform.finalize(soc)
-		src = verilog.convert(soc, ios)
+		so = {
+			NoRetiming:					XilinxNoRetiming,
+			MultiReg:					XilinxMultiReg,
+			AsyncResetSynchronizer:		XilinxAsyncResetSynchronizer
+		}
+		src = verilog.convert(soc, ios, special_overrides=so)
 		tools.write_to_file("build/litesata.v", src)
 
 	if actions["build-bitstream"]:
diff --git a/targets/bist.py b/targets/bist.py
index 348498e9..03cf31ed 100644
--- a/targets/bist.py
+++ b/targets/bist.py
@@ -62,6 +62,7 @@ class GenSoC(Module):
 	interrupt_map = {}
 	cpu_type = None
 	def __init__(self, platform, clk_freq):
+		self.clk_freq = clk_freq
 		# UART <--> Wishbone bridge
 		self.submodules.uart2wb = UART2Wishbone(platform.request("serial"), clk_freq, baud=921600)