From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 12 Feb 2015 19:39:29 +0000 (+0100)
Subject: simplify litescope export with do_exit call
X-Git-Tag: 24jan2021_ls180~2604^2~17
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4e4800e1b2461ea153ec513bd8b505dab12ef1b8;p=litex.git

simplify litescope export with do_exit call
---

diff --git a/make.py b/make.py
index 08d6e3b9..e95d14e2 100644
--- a/make.py
+++ b/make.py
@@ -117,7 +117,10 @@ System Clk: {} MHz
 		write_to_file(args.csr_csv, csr_csv)
 
 	if actions["build-bitstream"]:
-		platform.build(soc, build_name=build_name)
+		vns = platform.build(soc, build_name=build_name)
+		if hasattr(soc, "do_exit") and vns is not None:
+			if hasattr(soc.do_exit, '__call__'):
+				soc.do_exit(vns)
 
 	if actions["load-bitstream"]:
 		prog = platform.create_programmer()
diff --git a/targets/etherbone.py b/targets/etherbone.py
index 9b305bb5..90873665 100644
--- a/targets/etherbone.py
+++ b/targets/etherbone.py
@@ -1,4 +1,4 @@
-import os, atexit
+import os
 
 from migen.bank import csrgen
 from migen.bus import wishbone, csr
@@ -15,6 +15,7 @@ from litescope.frontend.la import LiteScopeLA
 from litescope.core.port import LiteScopeTerm
 
 from liteeth.common import *
+from liteeth.generic import *
 from liteeth.phy.gmii import LiteEthPHYGMII
 from liteeth.core import LiteEthUDPIPCore
 from liteeth.core.etherbone import LiteEthEtherbone
@@ -179,12 +180,10 @@ class EtherboneSoCDevel(EtherboneSoC, AutoCSR):
 
 		self.submodules.la = LiteScopeLA(debug, 4096)
 		self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
-		atexit.register(self.exit, platform)
 
 	def do_finalize(self):
 		EtherboneSoC.do_finalize(self)
 
-	def exit(self, platform):
-		if platform.vns is not None:
-			self.la.export(platform.vns, "../test/la.csv")
+	def do_exit(self, vns):
+		self.la.export(vns, "test/la.csv")
 default_subtarget = EtherboneSoC
diff --git a/targets/udp.py b/targets/udp.py
index 32d8ee9c..0a51e5e8 100644
--- a/targets/udp.py
+++ b/targets/udp.py
@@ -1,4 +1,4 @@
-import os, atexit
+import os
 
 from migen.bank import csrgen
 from migen.bus import wishbone, csr
@@ -15,6 +15,7 @@ from litescope.frontend.la import LiteScopeLA
 from litescope.core.port import LiteScopeTerm
 
 from liteeth.common import *
+from liteeth.generic import *
 from liteeth.phy.gmii import LiteEthPHYGMII
 from liteeth.core import LiteEthUDPIPCore
 
@@ -177,18 +178,6 @@ class UDPSoCDevel(UDPSoC, AutoCSR):
 			self.core.ip.crossbar.master.sink.ip_address,
 			self.core.ip.crossbar.master.sink.protocol,
 
-			self.loopback_buffer.sink.stb,
-			self.loopback_buffer.sink.sop,
-			self.loopback_buffer.sink.eop,
-			self.loopback_buffer.sink.ack,
-			self.loopback_buffer.sink.data,
-
-			self.loopback_buffer.source.stb,
-			self.loopback_buffer.source.sop,
-			self.loopback_buffer.source.eop,
-			self.loopback_buffer.source.ack,
-			self.loopback_buffer.source.data,
-
 			self.phy.sink.stb,
 			self.phy.sink.sop,
 			self.phy.sink.eop,
@@ -214,7 +203,6 @@ class UDPSoCDevel(UDPSoC, AutoCSR):
 
 		self.submodules.la = LiteScopeLA(debug, 4096)
 		self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
-		atexit.register(self.exit, platform)
 
 	def do_finalize(self):
 		UDPSoC.do_finalize(self)
@@ -230,8 +218,7 @@ class UDPSoCDevel(UDPSoC, AutoCSR):
 			self.core_arp_table_fsm_state.eq(self.core.arp.table.fsm.state)
 		]
 
-	def exit(self, platform):
-		if platform.vns is not None:
-			self.la.export(platform.vns, "../test/la.csv")
+	def do_exit(self, vns):
+		self.la.export(vns, "test/la.csv")
 
 default_subtarget = UDPSoC