From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 8 Oct 2020 22:36:35 +0000 (+0100)
Subject: missing yields in JTAG pads test to allow settling
X-Git-Tag: 24jan2021_ls180~173
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4e5996024f0dfeeaf441306c1c30d004db8213b7;p=soc.git

missing yields in JTAG pads test to allow settling
---

diff --git a/src/soc/debug/test/test_jtag_tap_srv.py b/src/soc/debug/test/test_jtag_tap_srv.py
index c2c273e0..25e2cdd4 100644
--- a/src/soc/debug/test/test_jtag_tap_srv.py
+++ b/src/soc/debug/test/test_jtag_tap_srv.py
@@ -73,6 +73,7 @@ def jtag_sim(dut, srv_dut):
 
     bs = yield from jtag_read_write_reg(dut, BS_SAMPLE, bslen, bs_actual)
     print ("bs scan", bin(bs))
+    yield
 
     print ("io0 pad.i", (yield srv_dut.ios[0].pad.i))
     print ("io1 core.o", (yield srv_dut.ios[1].core.o))