From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 21 Apr 2019 09:18:27 +0000 (+0100)
Subject: whoops, PTE bits wrong way round, make LSB to MSB
X-Git-Tag: div_pipeline~2206
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4e6777b51d139a85a3910a84e46acf5c3536ac01;p=soc.git

whoops, PTE bits wrong way round, make LSB to MSB
---

diff --git a/TLB/src/ariane/ptw.py b/TLB/src/ariane/ptw.py
index 4bbdea08..dec52af2 100644
--- a/TLB/src/ariane/ptw.py
+++ b/TLB/src/ariane/ptw.py
@@ -82,17 +82,17 @@ class DCacheReqO:
 
 class PTE: #(RecordObject):
     def __init__(self):
-        self.reserved = Signal(10)
-        self.ppn = Signal(44)
-        self.rsw = Signal(2)
-        self.d = Signal()
-        self.a = Signal()
-        self.g = Signal()
-        self.u = Signal()
-        self.x = Signal()
-        self.w = Signal()
-        self.r = Signal()
         self.v = Signal()
+        self.r = Signal()
+        self.w = Signal()
+        self.x = Signal()
+        self.u = Signal()
+        self.g = Signal()
+        self.a = Signal()
+        self.d = Signal()
+        self.rsw = Signal(2)
+        self.ppn = Signal(44)
+        self.reserved = Signal(10)
 
     def flatten(self):
         return Cat(*self.ports())
@@ -108,9 +108,23 @@ class PTE: #(RecordObject):
             x = x.flatten()
         return self.flatten().eq(x)
 
+    def __iter__(self):
+        """ order is critical so that flatten creates LSB to MSB
+        """
+        yield self.v
+        yield self.r
+        yield self.w
+        yield self.x
+        yield self.u
+        yield self.g
+        yield self.a
+        yield self.d
+        yield self.rsw
+        yield self.ppn
+        yield self.reserved
+
     def ports(self):
-        return [self.reserved, self.ppn, self.rsw, self.d, self.a, self.g,
-                self.u, self.x, self.w, self.r, self.v]
+        return list(self)
 
 
 class TLBUpdate:
diff --git a/TLB/src/ariane/test_ptw.py b/TLB/src/ariane/test_ptw.py
index 1a76e50c..a42a6da6 100644
--- a/TLB/src/ariane/test_ptw.py
+++ b/TLB/src/ariane/test_ptw.py
@@ -13,7 +13,7 @@ def testbench(dut):
 
     yield dut.req_port_i.data_gnt.eq(1)
     yield dut.req_port_i.data_rvalid.eq(1)
-    yield dut.req_port_i.data_rdata.eq(0xc2<<56)#pte.flatten())
+    yield dut.req_port_i.data_rdata.eq(0x43)#pte.flatten())
 
     # data lookup
     yield dut.en_ld_st_translation_i.eq(1)
@@ -51,7 +51,7 @@ def testbench(dut):
     yield dut.mxr_i.eq(0x1)
     yield dut.req_port_i.data_gnt.eq(1)
     yield dut.req_port_i.data_rvalid.eq(1)
-    yield dut.req_port_i.data_rdata.eq(0x82<<56 | addr<<2)#pte.flatten())
+    yield dut.req_port_i.data_rdata.eq(0x41 | (addr>>12)<<10)#pte.flatten())
 
     yield dut.en_ld_st_translation_i.eq(1)
     yield dut.asid_i.eq(1)