From: lkcl <lkcl@web>
Date: Wed, 6 Jan 2021 17:24:19 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~606
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4e757511737de3e597681bcc1b7bedc745cffc07;p=libreriscv.git

---

diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn
index a5655fcc0..4ff5882e1 100644
--- a/openpower/sv/bitmanip.mdwn
+++ b/openpower/sv/bitmanip.mdwn
@@ -26,7 +26,7 @@ for every bit perform a lookup into a table using an 8bit immediate
 
 | 0.5|6.10|11.15|16.20| 21..22 | 23...30 |31|  name   |
 | -- | -- | --- | --- | ------ | ------- |--| ------- |
-| NN | RT | RA  | RB  | M   0  | im[0:7] |Rc| XL-Form |
+| NN | RT | RA  | RB  | 0   0  | im[0:7] |Rc| XL-Form |
 
     for i in range(64):
         idx = RT[i] << 2 | RA[i] << 1 | RB[i]
@@ -34,6 +34,16 @@ for every bit perform a lookup into a table using an 8bit immediate
 
 bits 21..22 may be used to specify a mode, such as treating the whole integer zero/nonzero and putting 1/0 in the result, rather than bitwise test.
 
+a 4 operand variant which becomes more along the lines of an FPGA:
+
+| 0.5|6.10|11.15|16.20| 21..22 | 23...30 |31|  name   |
+| -- | -- | --- | --- | ------ | ------- |--| ------- |
+| NN | RT | RA  | RB  | 1   0  | RC ///  |Rc| XL-Form |
+
+    for i in range(64):
+        idx = RT[i] << 2 | RA[i] << 1 | RB[i]
+        RT[i] = (RC & (1<<idx)) != 0
+
 another mode selection would be CRs not Ints. 
 
 | 0.5|6.8 | 9.11|12.14|15.17|18.21|22 | 23...30 |31|  name   |
@@ -49,7 +59,7 @@ another mode selection would be CRs not Ints.
 
 # single bit set
 
-based on RV bitmanip
+based on RV bitmanip, instruction format similar to shift
 
 ```
 uint_xlen_t sbset(uint_xlen_t rs1, uint_xlen_t rs2) {