From: Anton Blanchard <anton@linux.ibm.com>
Date: Tue, 19 May 2020 02:28:02 +0000 (+1000)
Subject: Merge branch 'master' into litedram
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4e78b8078eec8d5bf13ae62882f0ce49207d724d;p=microwatt.git

Merge branch 'master' into litedram
---

4e78b8078eec8d5bf13ae62882f0ce49207d724d
diff --cc core.vhdl
index 0664c73,b0ccb7b..8ac724c
--- a/core.vhdl
+++ b/core.vhdl
@@@ -183,9 -169,10 +197,10 @@@ begi
              )
          port map(
              clk => clk,
 -            rst => icache_rst,
 +            rst => rst_icache,
              i_in => fetch1_to_icache,
              i_out => icache_to_fetch2,
+             m_in => mmu_to_icache,
              flush_in => flush,
  	    stall_out => icache_stall_out,
              wishbone_out => wishbone_insn_out,
@@@ -283,8 -278,9 +304,9 @@@
      loadstore1_0: entity work.loadstore1
          port map (
              clk => clk,
 -            rst => core_rst,
 +            rst => rst_ls1,
              l_in => execute1_to_loadstore1,
+             e_out => loadstore1_to_execute1,
              l_out => loadstore1_to_writeback,
              d_out => loadstore1_to_dcache,
              d_in => dcache_to_loadstore1,
@@@ -300,9 -309,11 +335,11 @@@
              )
          port map (
              clk => clk,
 -	    rst => core_rst,
 +	    rst => rst_dcache,
              d_in => loadstore1_to_dcache,
              d_out => dcache_to_loadstore1,
+             m_in => mmu_to_dcache,
+             m_out => dcache_to_mmu,
              stall_out => dcache_stall_out,
              wishbone_in => wishbone_data_in,
              wishbone_out => wishbone_data_out
diff --cc soc.vhdl
index e9e9470,899a71b..caa62cd
--- a/soc.vhdl
+++ b/soc.vhdl
@@@ -73,7 -73,8 +73,7 @@@ architecture behaviour of soc i
  
      -- Syscon signals
      signal dram_at_0     : std_ulogic;
--    signal core_reset    : std_ulogic;
+     signal do_core_reset : std_ulogic;
      signal wb_syscon_in  : wishbone_master_out;
      signal wb_syscon_out : wishbone_slave_out;
  
@@@ -109,34 -110,10 +109,34 @@@
      signal dmi_core_dout  : std_ulogic_vector(63 downto 0);
      signal dmi_core_req   : std_ulogic;
      signal dmi_core_ack   : std_ulogic;
 +
 +    -- Delayed/latched resets and alt_reset
 +    signal rst_core    : std_ulogic := '1';
 +    signal rst_uart    : std_ulogic := '1';
 +    signal rst_xics    : std_ulogic := '1';
 +    signal rst_bram    : std_ulogic := '1';
 +    signal rst_dtm     : std_ulogic := '1';
 +    signal rst_wbar    : std_ulogic := '1';
 +    signal rst_wbdb    : std_ulogic := '1';
 +    signal alt_reset_d : std_ulogic;
 +
  begin
  
 +    resets: process(system_clk)
 +    begin
 +        if rising_edge(system_clk) then
-             rst_core    <= rst or core_reset;
++            rst_core    <= rst or do_core_reset;
 +            rst_uart    <= rst;
 +            rst_xics    <= rst;
 +            rst_bram    <= rst;
 +            rst_dtm     <= rst;
 +            rst_wbar    <= rst;
 +            rst_wbdb    <= rst;
 +            alt_reset_d <= alt_reset;
 +        end if;
 +    end process;
 +
      -- Processor core
 -    core_reset <= rst or do_core_reset;
      processor: entity work.core
  	generic map(
  	    SIM => SIM,