From: Clifford Wolf Date: Wed, 23 Jul 2014 13:36:09 +0000 (+0200) Subject: Fixed all users of SigSpec::chunks_rw() and removed it X-Git-Tag: yosys-0.4~475 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4e802eb7f6fe5858f8657be7cd3e6638cc0f2ece;p=yosys.git Fixed all users of SigSpec::chunks_rw() and removed it --- diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 80007ab8c..e1c5b1a6b 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -533,7 +533,6 @@ public: SigSpec(std::vector bits); SigSpec(std::set bits); - inline std::vector &chunks_rw() { pack(); return chunks_; } inline const std::vector &chunks() const { pack(); return chunks_; } inline const std::vector &bits() const { inline_unpack(); return bits_; } @@ -597,7 +596,8 @@ public: static bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str); static bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); - operator std::vector() const { return to_sigbit_vector(); } + operator std::vector() const { return chunks(); } + operator std::vector() const { return bits(); } void check() const; }; diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc index f433c4b4a..7fe95b0a9 100644 --- a/passes/cmds/delete.cc +++ b/passes/cmds/delete.cc @@ -27,12 +27,13 @@ struct DeleteWireWorker std::set *delete_wires_p; void operator()(RTLIL::SigSpec &sig) { - sig.optimize(); - for (auto &c : sig.chunks_rw()) + std::vector chunks = sig; + for (auto &c : chunks) if (c.wire != NULL && delete_wires_p->count(c.wire->name)) { c.wire = module->addWire(NEW_ID, c.width); c.offset = 0; } + sig = chunks; } }; diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 619930b3a..63d5bb9af 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -23,35 +23,33 @@ #include "kernel/rtlil.h" #include "kernel/log.h" -static int next_bit_mode; -static uint32_t next_bit_state; - -static RTLIL::State next_bit() +struct SetundefWorker { - if (next_bit_mode == 0) - return RTLIL::State::S0; + int next_bit_mode; + uint32_t next_bit_state; - if (next_bit_mode == 1) - return RTLIL::State::S1; + RTLIL::State next_bit() + { + if (next_bit_mode == 0) + return RTLIL::State::S0; - // xorshift32 - next_bit_state ^= next_bit_state << 13; - next_bit_state ^= next_bit_state >> 17; - next_bit_state ^= next_bit_state << 5; - log_assert(next_bit_state != 0); + if (next_bit_mode == 1) + return RTLIL::State::S1; - return ((next_bit_state >> (next_bit_state & 15)) & 16) ? RTLIL::State::S0 : RTLIL::State::S1; -} + // xorshift32 + next_bit_state ^= next_bit_state << 13; + next_bit_state ^= next_bit_state >> 17; + next_bit_state ^= next_bit_state << 5; + log_assert(next_bit_state != 0); + + return ((next_bit_state >> (next_bit_state & 15)) & 16) ? RTLIL::State::S0 : RTLIL::State::S1; + } -struct SetundefWorker -{ void operator()(RTLIL::SigSpec &sig) { - sig.expand(); - for (auto &c : sig.chunks_rw()) - if (c.wire == NULL && c.data.bits.at(0) > RTLIL::State::S1) - c.data.bits.at(0) = next_bit(); - sig.optimize(); + for (auto &bit : sig) + if (bit.wire == NULL && bit.data > RTLIL::State::S1) + bit = next_bit(); } }; @@ -83,6 +81,7 @@ struct SetundefPass : public Pass { { bool got_value = false; bool undriven_mode = false; + SetundefWorker worker; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) @@ -93,20 +92,20 @@ struct SetundefPass : public Pass { } if (args[argidx] == "-zero") { got_value = true; - next_bit_mode = 0; + worker.next_bit_mode = 0; continue; } if (args[argidx] == "-one") { got_value = true; - next_bit_mode = 1; + worker.next_bit_mode = 1; continue; } if (args[argidx] == "-random" && !got_value && argidx+1 < args.size()) { got_value = true; - next_bit_mode = 2; - next_bit_state = atoi(args[++argidx].c_str()) + 1; + worker.next_bit_mode = 2; + worker.next_bit_state = atoi(args[++argidx].c_str()) + 1; for (int i = 0; i < 10; i++) - next_bit(); + worker.next_bit(); continue; } break; @@ -144,13 +143,13 @@ struct SetundefPass : public Pass { for (auto &c : sig.chunks()) { RTLIL::SigSpec bits; for (int i = 0; i < c.width; i++) - bits.append(next_bit()); + bits.append(worker.next_bit()); bits.optimize(); module->connections.push_back(RTLIL::SigSig(c, bits)); } } - module->rewrite_sigspecs(SetundefWorker()); + module->rewrite_sigspecs(worker); } } } SetundefPass; diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index d71e9727c..c40ff2c4a 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -62,11 +62,9 @@ struct SplitnetsWorker void operator()(RTLIL::SigSpec &sig) { - sig.expand(); - for (auto &c : sig.chunks_rw()) - if (splitmap.count(c.wire) > 0) - c = splitmap.at(c.wire).at(c.offset); - sig.optimize(); + for (auto &bit : sig) + if (splitmap.count(bit.wire) > 0) + bit = splitmap.at(bit.wire).at(bit.offset); } }; diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index b983a840e..257301880 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -164,10 +164,10 @@ struct SubmodWorker for (RTLIL::Cell *cell : submod.cells) { RTLIL::Cell *new_cell = new RTLIL::Cell(*cell); for (auto &conn : new_cell->connections) - for (auto &c : conn.second.chunks_rw()) - if (c.wire != NULL) { - assert(wire_flags.count(c.wire) > 0); - c.wire = wire_flags[c.wire].new_wire; + for (auto &bit : conn.second) + if (bit.wire != NULL) { + assert(wire_flags.count(bit.wire) > 0); + bit.wire = wire_flags[bit.wire].new_wire; } log(" cell %s (%s)\n", new_cell->name.c_str(), new_cell->type.c_str()); new_mod->cells[new_cell->name] = new_cell; diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index dee48597f..b1f1e22b5 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -32,13 +32,10 @@ static void normalize_sig(RTLIL::Module *module, RTLIL::SigSpec &sig) static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::SigSpec &clk, bool &clk_polarity, bool after = false) { normalize_sig(module, sig); - sig.expand(); - for (size_t i = 0; i < sig.chunks().size(); i++) + for (auto &bit : sig) { - RTLIL::SigChunk &chunk = sig.chunks_rw()[i]; - - if (chunk.wire == NULL) + if (bit.wire == NULL) continue; for (auto &cell_it : module->cells) @@ -58,12 +55,11 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI RTLIL::SigSpec q_norm = cell->connections[after ? "\\D" : "\\Q"]; normalize_sig(module, q_norm); - RTLIL::SigSpec d = q_norm.extract(chunk, &cell->connections[after ? "\\Q" : "\\D"]); + RTLIL::SigSpec d = q_norm.extract(bit, &cell->connections[after ? "\\Q" : "\\D"]); if (d.size() != 1) continue; - assert(d.chunks().size() == 1); - chunk = d.chunks()[0]; + bit = d; clk = cell->connections["\\CLK"]; clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool(); goto replaced_this_bit; diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index 6cb560f5c..145abfa43 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -165,11 +165,9 @@ restart_proc_arst: for (auto &action : sync->actions) { RTLIL::SigSpec rspec = action.second; RTLIL::SigSpec rval = RTLIL::SigSpec(RTLIL::State::Sm, rspec.size()); - rspec.expand(), rval.expand(); - for (int i = 0; i < int(rspec.chunks().size()); i++) - if (rspec.chunks()[i].wire == NULL) - rval.chunks_rw()[i] = rspec.chunks()[i]; - rspec.optimize(), rval.optimize(); + for (int i = 0; i < SIZE(rspec); i++) + if (rspec[i].wire == NULL) + rval[i] = rspec[i]; RTLIL::SigSpec last_rval; for (int count = 0; rval != last_rval; count++) { last_rval = rval; diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 902dedb62..090f7463a 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -70,11 +70,9 @@ struct BruteForceEquivChecker log_signal(undef2), log_signal(mod1_inputs), log_signal(inputs)); if (ignore_x_mod1) { - sig1.expand(), sig2.expand(); - for (size_t i = 0; i < sig1.chunks().size(); i++) - if (sig1.chunks().at(i) == RTLIL::SigChunk(RTLIL::State::Sx)) - sig2.chunks_rw().at(i) = RTLIL::SigChunk(RTLIL::State::Sx); - sig1.optimize(), sig2.optimize(); + for (int i = 0; i < SIZE(sig1); i++) + if (sig1[i] == RTLIL::State::Sx) + sig2[i] = RTLIL::State::Sx; } if (sig1 != sig2) { @@ -297,9 +295,9 @@ struct VlogHammerReporter sig.expand(); if (rtl_sig.size() != sig.size()) log_error("Output (y) has a different width in module %s compared to rtl!\n", RTLIL::id2cstr(module->name)); - for (int i = 0; i < sig.size(); i++) - if (rtl_sig.chunks().at(i).data.bits.at(0) == RTLIL::State::Sx) - sig.chunks_rw().at(i).data.bits.at(0) = RTLIL::State::Sx; + for (int i = 0; i < SIZE(sig); i++) + if (rtl_sig[i] == RTLIL::State::Sx) + sig[i] = RTLIL::State::Sx; } log("++RPT++ %d%s %s %s\n", idx, input_pattern_list.c_str(), sig.as_const().as_string().c_str(), module_name.c_str()); diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 1687a1ffb..e5055c9c4 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -755,11 +755,11 @@ struct ExtractPass : public Pass { newCell->type = cell->type; newCell->parameters = cell->parameters; for (auto &conn : cell->connections) { - RTLIL::SigSpec sig = sigmap(conn.second); - for (auto &chunk : sig.chunks_rw()) + std::vector chunks = sigmap(conn.second); + for (auto &chunk : chunks) if (chunk.wire != NULL) chunk.wire = newMod->wires.at(chunk.wire->name); - newCell->connections[conn.first] = sig; + newCell->connections[conn.first] = chunks; } newMod->add(newCell); } diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc index 53c5d1044..51b8802c4 100644 --- a/passes/techmap/hilomap.cc +++ b/passes/techmap/hilomap.cc @@ -26,36 +26,34 @@ static std::string locell_celltype, locell_portname; static bool singleton_mode; static RTLIL::Module *module; -static RTLIL::SigChunk last_hi, last_lo; +static RTLIL::SigBit last_hi, last_lo; void hilomap_worker(RTLIL::SigSpec &sig) { - sig.expand(); - for (auto &c : sig.chunks_rw()) { - if (c.wire == NULL && (c.data.bits.at(0) == RTLIL::State::S1) && !hicell_celltype.empty()) { - if (!singleton_mode || last_hi.width == 0) { - last_hi = RTLIL::SigChunk(module->addWire(NEW_ID)); + for (auto &bit : sig) { + if (bit == RTLIL::State::S1 && !hicell_celltype.empty()) { + if (!singleton_mode || last_hi == RTLIL::State::Sm) { + last_hi = module->addWire(NEW_ID); RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = RTLIL::escape_id(hicell_celltype); cell->connections[RTLIL::escape_id(hicell_portname)] = last_hi; module->add(cell); } - c = last_hi; + bit = last_hi; } - if (c.wire == NULL && (c.data.bits.at(0) == RTLIL::State::S0) && !locell_celltype.empty()) { - if (!singleton_mode || last_lo.width == 0) { - last_lo = RTLIL::SigChunk(module->addWire(NEW_ID)); + if (bit == RTLIL::State::S0 && !locell_celltype.empty()) { + if (!singleton_mode || last_lo == RTLIL::State::Sm) { + last_lo = module->addWire(NEW_ID); RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = RTLIL::escape_id(locell_celltype); cell->connections[RTLIL::escape_id(locell_portname)] = last_lo; module->add(cell); } - c = last_lo; + bit = last_lo; } } - sig.optimize(); } struct HilomapPass : public Pass { @@ -119,8 +117,8 @@ struct HilomapPass : public Pass { if (!design->selected(module)) continue; - last_hi = RTLIL::SigChunk(); - last_lo = RTLIL::SigChunk(); + last_hi = RTLIL::State::Sm; + last_lo = RTLIL::State::Sm; module->rewrite_sigspecs(hilomap_worker); } diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index f3b1a0ef7..8d7b21e0f 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -41,14 +41,15 @@ static void apply_prefix(std::string prefix, std::string &id) static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module *module) { - for (size_t i = 0; i < sig.chunks().size(); i++) { - if (sig.chunks()[i].wire == NULL) - continue; - std::string wire_name = sig.chunks()[i].wire->name; - apply_prefix(prefix, wire_name); - assert(module->wires.count(wire_name) > 0); - sig.chunks_rw()[i].wire = module->wires[wire_name]; - } + std::vector chunks = sig; + for (auto &chunk : chunks) + if (chunk.wire != NULL) { + std::string wire_name = chunk.wire->name; + apply_prefix(prefix, wire_name); + assert(module->wires.count(wire_name) > 0); + chunk.wire = module->wires[wire_name]; + } + sig = chunks; } struct TechmapWorker