From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 4 Aug 2019 11:34:38 +0000 (+0100)
Subject: added maskwidth and dynamic use of MaskCancellable, no "bugs", still to
X-Git-Tag: ls180-24jan2020~550
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4e8344afa95ff5510b6d3e5e29783067308e7674;p=ieee754fpu.git

added maskwidth and dynamic use of MaskCancellable, no "bugs", still to
confirm if it works
---

diff --git a/src/ieee754/fpdiv/pipeline.py b/src/ieee754/fpdiv/pipeline.py
index 42f7d1b0..9bfcb49e 100644
--- a/src/ieee754/fpdiv/pipeline.py
+++ b/src/ieee754/fpdiv/pipeline.py
@@ -74,12 +74,13 @@ from ieee754.fpdiv.divstages import (FPDivStagesSetup,
                                      FPDivStagesFinal)
 from ieee754.pipeline import PipelineSpec
 from ieee754.div_rem_sqrt_rsqrt.core import DivPipeCoreConfig
+from nmutil.dynamicpipe import MaskCancellableRedir
 
 
 class FPDIVBasePipe(ControlBase):
     def __init__(self, pspec):
         self.pspec = pspec
-        ControlBase.__init__(self)
+        ControlBase.__init__(self, maskwid=pspec.maskwid)
 
         pipechain = []
         # to which the answer: "as few as possible"
@@ -164,6 +165,7 @@ class FPDIVMuxInOut(ReservationStations):
         fmt = FPFormat.standard(width)
         log2_radix = 3     # tested options so far: 1, 2 and 3.
         n_comb_stages = 2  # 2 compute stages per pipeline stage
+        maskwid = 1        # SIMD width effectively
 
         # extra bits needed: guard + round (sticky comes from remainer.bool())
         fraction_width = fmt.fraction_width
@@ -174,6 +176,8 @@ class FPDIVMuxInOut(ReservationStations):
         # the last stage
         cfg = DivPipeCoreConfig(fmt.width, fraction_width, log2_radix)
 
+        self.pspec.pipekls = MaskCancellableRedir
+        self.pspec.maskwid = maskwid
         self.pspec.fpformat = fmt
         self.pspec.n_comb_stages = n_comb_stages
         self.pspec.core_config = cfg
@@ -184,4 +188,4 @@ class FPDIVMuxInOut(ReservationStations):
         # new_pspec.opkls = DivPipeCoreOperation
         # self.alu = FPDIVBasePipe(new_pspec)
         self.alu = FPDIVBasePipe(self.pspec)
-        ReservationStations.__init__(self, num_rows)
+        ReservationStations.__init__(self, num_rows, maskwid=maskwid)
diff --git a/src/nmutil/concurrentunit.py b/src/nmutil/concurrentunit.py
index a04f5769..da63d322 100644
--- a/src/nmutil/concurrentunit.py
+++ b/src/nmutil/concurrentunit.py
@@ -22,17 +22,19 @@ def num_bits(n):
 
 
 class FPADDInMuxPipe(PriorityCombMuxInPipe):
-    def __init__(self, num_rows, iospecfn):
+    def __init__(self, num_rows, iospecfn, maskwid=0):
         self.num_rows = num_rows
         stage = PassThroughStage(iospecfn)
-        PriorityCombMuxInPipe.__init__(self, stage, p_len=self.num_rows)
+        PriorityCombMuxInPipe.__init__(self, stage, p_len=self.num_rows,
+                                       maskwid=maskwid)
 
 
 class FPADDMuxOutPipe(CombMuxOutPipe):
-    def __init__(self, num_rows, iospecfn):
+    def __init__(self, num_rows, iospecfn, maskwid=0):
         self.num_rows = num_rows
         stage = PassThroughStage(iospecfn)
-        CombMuxOutPipe.__init__(self, stage, n_len=self.num_rows)
+        CombMuxOutPipe.__init__(self, stage, n_len=self.num_rows,
+                                maskwid=maskwid)
 
 
 class ReservationStations(Elaboratable):
@@ -49,10 +51,10 @@ class ReservationStations(Elaboratable):
 
         Fan-in and Fan-out are combinatorial.
     """
-    def __init__(self, num_rows):
-        self.num_rows = num_rows
-        self.inpipe = FPADDInMuxPipe(num_rows, self.i_specfn)   # fan-in
-        self.outpipe = FPADDMuxOutPipe(num_rows, self.o_specfn) # fan-out
+    def __init__(self, num_rows, maskwid=0):
+        self.num_rows = nr = num_rows
+        self.inpipe = FPADDInMuxPipe(nr, self.i_specfn, maskwid)   # fan-in
+        self.outpipe = FPADDMuxOutPipe(nr, self.o_specfn, maskwid) # fan-out
 
         self.p = self.inpipe.p  # kinda annoying,
         self.n = self.outpipe.n # use pipe in/out as this class in/out
diff --git a/src/nmutil/dynamicpipe.py b/src/nmutil/dynamicpipe.py
index b6eb2a7e..aaba4a6a 100644
--- a/src/nmutil/dynamicpipe.py
+++ b/src/nmutil/dynamicpipe.py
@@ -16,6 +16,8 @@ understand (meta-class programming).
 from abc import ABCMeta
 
 from nmutil.singlepipe import SimpleHandshake
+from nmutil.singlepipe import MaskCancellable
+
 import threading
 
 # with many thanks to jsbueno on stackexchange for this one
@@ -86,3 +88,13 @@ class SimpleHandshakeRedir(SimpleHandshake):
             stage = args[0].stage
         SimpleHandshake.__init__(self, stage)
 
+
+class MaskCancellableRedir(SimpleHandshake):
+    def __init__(self, mod, *args):
+        stage = self
+        maskwid = args[0].maskwid
+        if args[0].stage:
+            stage = args[0].stage
+        print ("redir mask", mod, args, maskwid)
+        MaskCancellable.__init__(self, stage, maskwid)
+