From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 22 Mar 2020 14:30:29 +0000 (+0000)
Subject: dont have to but test latchregister incoming is a Record
X-Git-Tag: 24jan2021_ls180~79
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4e8677e306016a7f04721242385d4703569c6cb3;p=nmutil.git

dont have to but test latchregister incoming is a Record
---

diff --git a/src/nmutil/latch.py b/src/nmutil/latch.py
index 5f3a0c0..7d6a1ef 100644
--- a/src/nmutil/latch.py
+++ b/src/nmutil/latch.py
@@ -1,6 +1,6 @@
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
-from nmigen import Signal, Module, Const, Elaboratable
+from nmigen import Record, Signal, Module, Const, Elaboratable
 
 """ jk latch
 
@@ -22,7 +22,11 @@ endmodule
 """
 
 def latchregister(m, incoming, outgoing, settrue, name=None):
-    reg = Signal.like(incoming, name=name) # make reg same as input. reset OK.
+    # make reg same as input. reset OK.
+    if isinstance(incoming, Record):
+        reg = Record.like(incoming, name=name)
+    else:
+        reg = Signal.like(incoming, name=name)
     with m.If(settrue): # pass in some kind of expression/condition here
         m.d.sync += reg.eq(incoming)      # latch input into register
         m.d.comb += outgoing.eq(incoming) # return input (combinatorial)