From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 1 Apr 2021 22:41:07 +0000 (+0000)
Subject: update / refresh full core DFF
X-Git-Tag: LS180_RC3~159
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4e8f0957917307f5bba7466c336d2eade537811a;p=soclayout.git

update / refresh full core DFF
---

diff --git a/experiments9/non_generated/full_core_ls180.il b/experiments9/non_generated/full_core_ls180.il
index 5fb3a42..63afd5b 100644
--- a/experiments9/non_generated/full_core_ls180.il
+++ b/experiments9/non_generated/full_core_ls180.il
@@ -238810,13 +238810,13 @@ module \ls180
   wire $0\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0]
   attribute \src "ls180.v:4169.1-4274.4"
   wire $0\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0]
-  attribute \src "ls180.v:133.5-133.64"
+  attribute \src "ls180.v:121.5-121.64"
   wire $0\libresocsim_libresoc_constraintmanager_spimaster_clk[0:0]
-  attribute \src "ls180.v:135.5-135.65"
+  attribute \src "ls180.v:123.5-123.65"
   wire $0\libresocsim_libresoc_constraintmanager_spimaster_cs_n[0:0]
-  attribute \src "ls180.v:134.5-134.65"
+  attribute \src "ls180.v:122.5-122.65"
   wire $0\libresocsim_libresoc_constraintmanager_spimaster_mosi[0:0]
-  attribute \src "ls180.v:117.5-117.58"
+  attribute \src "ls180.v:133.5-133.58"
   wire $0\libresocsim_libresoc_constraintmanager_uart_rx[0:0]
   attribute \src "ls180.v:4276.1-5486.4"
   wire $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0]
@@ -239896,33 +239896,33 @@ module \ls180
   wire width 8 $1\libresocsim_interface6_bank_bus_dat_r[7:0]
   attribute \src "ls180.v:1307.11-1307.55"
   wire width 8 $1\libresocsim_interface7_bank_bus_dat_r[7:0]
-  attribute \src "ls180.v:131.12-131.65"
+  attribute \src "ls180.v:130.12-130.65"
   wire width 16 $1\libresocsim_libresoc_constraintmanager_gpio_o[15:0]
-  attribute \src "ls180.v:132.12-132.66"
+  attribute \src "ls180.v:131.12-131.66"
   wire width 16 $1\libresocsim_libresoc_constraintmanager_gpio_oe[15:0]
-  attribute \src "ls180.v:118.12-118.66"
+  attribute \src "ls180.v:109.12-109.66"
   wire width 13 $1\libresocsim_libresoc_constraintmanager_sdram_a[12:0]
-  attribute \src "ls180.v:127.11-127.65"
+  attribute \src "ls180.v:118.11-118.65"
   wire width 2 $1\libresocsim_libresoc_constraintmanager_sdram_ba[1:0]
-  attribute \src "ls180.v:124.5-124.62"
+  attribute \src "ls180.v:115.5-115.62"
   wire $1\libresocsim_libresoc_constraintmanager_sdram_cas_n[0:0]
-  attribute \src "ls180.v:126.5-126.60"
+  attribute \src "ls180.v:117.5-117.60"
   wire $1\libresocsim_libresoc_constraintmanager_sdram_cke[0:0]
-  attribute \src "ls180.v:129.5-129.62"
+  attribute \src "ls180.v:120.5-120.62"
   wire $1\libresocsim_libresoc_constraintmanager_sdram_clock[0:0]
-  attribute \src "ls180.v:125.5-125.61"
+  attribute \src "ls180.v:116.5-116.61"
   wire $1\libresocsim_libresoc_constraintmanager_sdram_cs_n[0:0]
-  attribute \src "ls180.v:128.11-128.65"
+  attribute \src "ls180.v:119.11-119.65"
   wire width 2 $1\libresocsim_libresoc_constraintmanager_sdram_dm[1:0]
-  attribute \src "ls180.v:120.12-120.69"
+  attribute \src "ls180.v:111.12-111.69"
   wire width 16 $1\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0]
-  attribute \src "ls180.v:121.5-121.62"
+  attribute \src "ls180.v:112.5-112.62"
   wire $1\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0]
-  attribute \src "ls180.v:123.5-123.62"
+  attribute \src "ls180.v:114.5-114.62"
   wire $1\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0]
-  attribute \src "ls180.v:122.5-122.61"
+  attribute \src "ls180.v:113.5-113.61"
   wire $1\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0]
-  attribute \src "ls180.v:116.5-116.58"
+  attribute \src "ls180.v:132.5-132.58"
   wire $1\libresocsim_libresoc_constraintmanager_uart_tx[0:0]
   attribute \src "ls180.v:59.5-59.41"
   wire $1\libresocsim_libresoc_dbus_ack[0:0]
@@ -243424,12 +243424,12 @@ module \ls180
   wire width 2 \dfi_p0_wrdata_mask
   attribute \src "ls180.v:993.12-993.17"
   wire width 40 \dummy
-  attribute \src "ls180.v:5.13-5.19"
-  wire input 1 \eint_0
-  attribute \src "ls180.v:6.13-6.19"
-  wire input 2 \eint_1
-  attribute \src "ls180.v:7.13-7.19"
-  wire input 3 \eint_2
+  attribute \src "ls180.v:30.13-30.19"
+  wire input 26 \eint_0
+  attribute \src "ls180.v:31.13-31.19"
+  wire input 27 \eint_1
+  attribute \src "ls180.v:32.13-32.19"
+  wire input 28 \eint_2
   attribute \src "ls180.v:991.11-991.19"
   wire width 3 \eint_tmp
   attribute \src "ls180.v:879.12-879.34"
@@ -243488,30 +243488,30 @@ module \ls180
   wire width 8 \gpio1_status
   attribute \src "ls180.v:985.6-985.14"
   wire \gpio1_we
-  attribute \src "ls180.v:26.20-26.26"
-  wire width 16 input 22 \gpio_i
-  attribute \src "ls180.v:27.21-27.27"
-  wire width 16 output 23 \gpio_o
-  attribute \src "ls180.v:28.21-28.28"
-  wire width 16 output 24 \gpio_oe
+  attribute \src "ls180.v:25.20-25.26"
+  wire width 16 input 21 \gpio_i
+  attribute \src "ls180.v:26.21-26.27"
+  wire width 16 output 22 \gpio_o
+  attribute \src "ls180.v:27.21-27.28"
+  wire width 16 output 23 \gpio_oe
   attribute \src "ls180.v:995.6-995.12"
   wire \i2c_oe
   attribute \src "ls180.v:998.5-998.11"
   wire \i2c_re
-  attribute \src "ls180.v:8.14-8.21"
-  wire output 4 \i2c_scl
+  attribute \src "ls180.v:21.14-21.21"
+  wire output 17 \i2c_scl
   attribute \src "ls180.v:994.6-994.15"
   wire \i2c_scl_1
   attribute \src "ls180.v:996.6-996.14"
   wire \i2c_sda0
   attribute \src "ls180.v:999.6-999.14"
   wire \i2c_sda1
-  attribute \src "ls180.v:9.13-9.22"
-  wire input 5 \i2c_sda_i
-  attribute \src "ls180.v:10.14-10.23"
-  wire output 6 \i2c_sda_o
-  attribute \src "ls180.v:11.14-11.24"
-  wire output 7 \i2c_sda_oe
+  attribute \src "ls180.v:22.13-22.22"
+  wire input 18 \i2c_sda_i
+  attribute \src "ls180.v:23.14-23.23"
+  wire output 19 \i2c_sda_o
+  attribute \src "ls180.v:24.14-24.24"
+  wire output 20 \i2c_sda_oe
   attribute \src "ls180.v:1000.6-1000.16"
   wire \i2c_status
   attribute \src "ls180.v:997.11-997.22"
@@ -244174,61 +244174,61 @@ module \ls180
   wire \libresocsim_libresoc1
   attribute \src "ls180.v:108.13-108.34"
   wire width 64 \libresocsim_libresoc2
-  attribute \src "ls180.v:109.6-109.51"
+  attribute \src "ls180.v:134.6-134.51"
   wire \libresocsim_libresoc_constraintmanager_eint_0
-  attribute \src "ls180.v:110.6-110.51"
+  attribute \src "ls180.v:135.6-135.51"
   wire \libresocsim_libresoc_constraintmanager_eint_1
-  attribute \src "ls180.v:111.6-111.51"
+  attribute \src "ls180.v:136.6-136.51"
   wire \libresocsim_libresoc_constraintmanager_eint_2
-  attribute \src "ls180.v:130.13-130.58"
+  attribute \src "ls180.v:129.13-129.58"
   wire width 16 \libresocsim_libresoc_constraintmanager_gpio_i
-  attribute \src "ls180.v:131.12-131.57"
+  attribute \src "ls180.v:130.12-130.57"
   wire width 16 \libresocsim_libresoc_constraintmanager_gpio_o
-  attribute \src "ls180.v:132.12-132.58"
+  attribute \src "ls180.v:131.12-131.58"
   wire width 16 \libresocsim_libresoc_constraintmanager_gpio_oe
-  attribute \src "ls180.v:112.6-112.52"
+  attribute \src "ls180.v:125.6-125.52"
   wire \libresocsim_libresoc_constraintmanager_i2c_scl
-  attribute \src "ls180.v:113.6-113.54"
+  attribute \src "ls180.v:126.6-126.54"
   wire \libresocsim_libresoc_constraintmanager_i2c_sda_i
-  attribute \src "ls180.v:114.6-114.54"
+  attribute \src "ls180.v:127.6-127.54"
   wire \libresocsim_libresoc_constraintmanager_i2c_sda_o
-  attribute \src "ls180.v:115.6-115.55"
+  attribute \src "ls180.v:128.6-128.55"
   wire \libresocsim_libresoc_constraintmanager_i2c_sda_oe
-  attribute \src "ls180.v:118.12-118.58"
+  attribute \src "ls180.v:109.12-109.58"
   wire width 13 \libresocsim_libresoc_constraintmanager_sdram_a
-  attribute \src "ls180.v:127.11-127.58"
+  attribute \src "ls180.v:118.11-118.58"
   wire width 2 \libresocsim_libresoc_constraintmanager_sdram_ba
-  attribute \src "ls180.v:124.5-124.55"
+  attribute \src "ls180.v:115.5-115.55"
   wire \libresocsim_libresoc_constraintmanager_sdram_cas_n
-  attribute \src "ls180.v:126.5-126.53"
+  attribute \src "ls180.v:117.5-117.53"
   wire \libresocsim_libresoc_constraintmanager_sdram_cke
-  attribute \src "ls180.v:129.5-129.55"
+  attribute \src "ls180.v:120.5-120.55"
   wire \libresocsim_libresoc_constraintmanager_sdram_clock
-  attribute \src "ls180.v:125.5-125.54"
+  attribute \src "ls180.v:116.5-116.54"
   wire \libresocsim_libresoc_constraintmanager_sdram_cs_n
-  attribute \src "ls180.v:128.11-128.58"
+  attribute \src "ls180.v:119.11-119.58"
   wire width 2 \libresocsim_libresoc_constraintmanager_sdram_dm
-  attribute \src "ls180.v:119.13-119.62"
+  attribute \src "ls180.v:110.13-110.62"
   wire width 16 \libresocsim_libresoc_constraintmanager_sdram_dq_i
-  attribute \src "ls180.v:120.12-120.61"
+  attribute \src "ls180.v:111.12-111.61"
   wire width 16 \libresocsim_libresoc_constraintmanager_sdram_dq_o
-  attribute \src "ls180.v:121.5-121.55"
+  attribute \src "ls180.v:112.5-112.55"
   wire \libresocsim_libresoc_constraintmanager_sdram_dq_oe
-  attribute \src "ls180.v:123.5-123.55"
+  attribute \src "ls180.v:114.5-114.55"
   wire \libresocsim_libresoc_constraintmanager_sdram_ras_n
-  attribute \src "ls180.v:122.5-122.54"
+  attribute \src "ls180.v:113.5-113.54"
   wire \libresocsim_libresoc_constraintmanager_sdram_we_n
-  attribute \src "ls180.v:133.5-133.57"
+  attribute \src "ls180.v:121.5-121.57"
   wire \libresocsim_libresoc_constraintmanager_spimaster_clk
-  attribute \src "ls180.v:135.5-135.58"
+  attribute \src "ls180.v:123.5-123.58"
   wire \libresocsim_libresoc_constraintmanager_spimaster_cs_n
-  attribute \src "ls180.v:136.6-136.59"
+  attribute \src "ls180.v:124.6-124.59"
   wire \libresocsim_libresoc_constraintmanager_spimaster_miso
-  attribute \src "ls180.v:134.5-134.58"
+  attribute \src "ls180.v:122.5-122.58"
   wire \libresocsim_libresoc_constraintmanager_spimaster_mosi
-  attribute \src "ls180.v:117.5-117.51"
+  attribute \src "ls180.v:133.5-133.51"
   wire \libresocsim_libresoc_constraintmanager_uart_rx
-  attribute \src "ls180.v:116.5-116.51"
+  attribute \src "ls180.v:132.5-132.51"
   wire \libresocsim_libresoc_constraintmanager_uart_tx
   attribute \src "ls180.v:59.5-59.34"
   wire \libresocsim_libresoc_dbus_ack
@@ -244750,14 +244750,14 @@ module \ls180
   wire width 8 \rxtx_w
   attribute \src "ls180.v:857.6-857.13"
   wire \rxtx_we
-  attribute \src "ls180.v:14.21-14.28"
-  wire width 13 output 10 \sdram_a
+  attribute \src "ls180.v:5.21-5.28"
+  wire width 13 output 1 \sdram_a
   attribute \src "ls180.v:321.5-321.21"
   wire \sdram_address_re
   attribute \src "ls180.v:320.12-320.33"
   wire width 13 \sdram_address_storage
-  attribute \src "ls180.v:23.20-23.28"
-  wire width 2 output 19 \sdram_ba
+  attribute \src "ls180.v:14.20-14.28"
+  wire width 2 output 10 \sdram_ba
   attribute \src "ls180.v:323.5-323.22"
   wire \sdram_baddress_re
   attribute \src "ls180.v:322.11-322.33"
@@ -245432,8 +245432,8 @@ module \ls180
   wire \sdram_bankmachine3_twtpcon_valid
   attribute \src "ls180.v:729.6-729.23"
   wire \sdram_cas_allowed
-  attribute \src "ls180.v:20.14-20.25"
-  wire output 16 \sdram_cas_n
+  attribute \src "ls180.v:11.14-11.25"
+  wire output 7 \sdram_cas_n
   attribute \src "ls180.v:747.6-747.25"
   wire \sdram_choose_cmd_ce
   attribute \src "ls180.v:736.13-736.43"
@@ -245506,12 +245506,12 @@ module \ls180
   wire \sdram_choose_req_want_reads
   attribute \src "ls180.v:749.5-749.33"
   wire \sdram_choose_req_want_writes
-  attribute \src "ls180.v:22.14-22.23"
-  wire output 18 \sdram_cke
+  attribute \src "ls180.v:13.14-13.23"
+  wire output 9 \sdram_cke
   attribute \src "ls180.v:309.6-309.17"
   wire \sdram_cke_1
-  attribute \src "ls180.v:25.14-25.25"
-  wire output 21 \sdram_clock
+  attribute \src "ls180.v:16.14-16.25"
+  wire output 12 \sdram_clock
   attribute \src "ls180.v:377.5-377.19"
   wire \sdram_cmd_last
   attribute \src "ls180.v:378.12-378.31"
@@ -245544,8 +245544,8 @@ module \ls180
   wire \sdram_command_re
   attribute \src "ls180.v:314.11-314.32"
   wire width 6 \sdram_command_storage
-  attribute \src "ls180.v:21.14-21.24"
-  wire output 17 \sdram_cs_n
+  attribute \src "ls180.v:12.14-12.24"
+  wire output 8 \sdram_cs_n
   attribute \src "ls180.v:368.5-368.23"
   wire \sdram_dfi_p0_act_n
   attribute \src "ls180.v:359.12-359.32"
@@ -245578,14 +245578,14 @@ module \ls180
   wire \sdram_dfi_p0_wrdata_en
   attribute \src "ls180.v:371.12-371.36"
   wire width 2 \sdram_dfi_p0_wrdata_mask
-  attribute \src "ls180.v:24.20-24.28"
-  wire width 2 output 20 \sdram_dm
-  attribute \src "ls180.v:15.20-15.30"
-  wire width 16 input 11 \sdram_dq_i
-  attribute \src "ls180.v:16.21-16.31"
-  wire width 16 output 12 \sdram_dq_o
-  attribute \src "ls180.v:17.14-17.25"
-  wire output 13 \sdram_dq_oe
+  attribute \src "ls180.v:15.20-15.28"
+  wire width 2 output 11 \sdram_dm
+  attribute \src "ls180.v:6.20-6.30"
+  wire width 16 input 2 \sdram_dq_i
+  attribute \src "ls180.v:7.21-7.31"
+  wire width 16 output 3 \sdram_dq_o
+  attribute \src "ls180.v:8.14-8.25"
+  wire output 4 \sdram_dq_oe
   attribute \src "ls180.v:783.5-783.14"
   wire \sdram_en0
   attribute \src "ls180.v:786.5-786.14"
@@ -245736,8 +245736,8 @@ module \ls180
   wire \sdram_postponer_req_o
   attribute \src "ls180.v:728.6-728.23"
   wire \sdram_ras_allowed
-  attribute \src "ls180.v:19.14-19.25"
-  wire output 15 \sdram_ras_n
+  attribute \src "ls180.v:10.14-10.25"
+  wire output 6 \sdram_ras_n
   attribute \src "ls180.v:313.5-313.13"
   wire \sdram_re
   attribute \src "ls180.v:781.6-781.26"
@@ -245842,8 +245842,8 @@ module \ls180
   wire \sdram_wants_refresh
   attribute \src "ls180.v:327.6-327.14"
   wire \sdram_we
-  attribute \src "ls180.v:18.14-18.24"
-  wire output 14 \sdram_we_n
+  attribute \src "ls180.v:9.14-9.24"
+  wire output 5 \sdram_we_n
   attribute \src "ls180.v:325.5-325.20"
   wire \sdram_wrdata_re
   attribute \src "ls180.v:324.12-324.32"
@@ -246058,14 +246058,14 @@ module \ls180
   wire \sdrio_clk_98
   attribute \src "ls180.v:1483.6-1483.18"
   wire \sdrio_clk_99
-  attribute \src "ls180.v:29.14-29.27"
-  wire output 25 \spimaster_clk
-  attribute \src "ls180.v:31.14-31.28"
-  wire output 27 \spimaster_cs_n
-  attribute \src "ls180.v:32.13-32.27"
-  wire input 28 \spimaster_miso
-  attribute \src "ls180.v:30.14-30.28"
-  wire output 26 \spimaster_mosi
+  attribute \src "ls180.v:17.14-17.27"
+  wire output 13 \spimaster_clk
+  attribute \src "ls180.v:19.14-19.28"
+  wire output 15 \spimaster_cs_n
+  attribute \src "ls180.v:20.13-20.27"
+  wire input 16 \spimaster_miso
+  attribute \src "ls180.v:18.14-18.28"
+  wire output 14 \spimaster_mosi
   attribute \src "ls180.v:1017.11-1017.47"
   wire width 3 \subfragments_bankmachine0_next_state
   attribute \src "ls180.v:1016.11-1016.42"
@@ -246308,8 +246308,8 @@ module \ls180
   wire \uart_phy_uart_clk_rxen
   attribute \src "ls180.v:838.5-838.27"
   wire \uart_phy_uart_clk_txen
-  attribute \src "ls180.v:13.13-13.20"
-  wire input 9 \uart_rx
+  attribute \src "ls180.v:29.13-29.20"
+  wire input 25 \uart_rx
   attribute \src "ls180.v:890.6-890.21"
   wire \uart_sink_first
   attribute \src "ls180.v:891.6-891.20"
@@ -246330,8 +246330,8 @@ module \ls180
   wire \uart_source_ready
   attribute \src "ls180.v:893.6-893.23"
   wire \uart_source_valid
-  attribute \src "ls180.v:12.13-12.20"
-  wire input 8 \uart_tx
+  attribute \src "ls180.v:28.13-28.20"
+  wire input 24 \uart_tx
   attribute \src "ls180.v:809.5-809.17"
   wire \wb_sdram_ack
   attribute \src "ls180.v:803.13-803.25"
@@ -261181,141 +261181,157 @@ module \ls180
     sync init
       update \libresocsim_interface0_bank_bus_dat_r $1\libresocsim_interface0_bank_bus_dat_r[7:0]
   end
-  attribute \src "ls180.v:1129.11-1129.55"
-  process $proc$ls180.v:1129$1999
+  attribute \src "ls180.v:109.12-109.66"
+  process $proc$ls180.v:109$1563
     assign { } { }
-    assign $1\libresocsim_interface1_bank_bus_dat_r[7:0] 8'00000000
+    assign $1\libresocsim_libresoc_constraintmanager_sdram_a[12:0] 13'0000000000000
     sync always
     sync init
-      update \libresocsim_interface1_bank_bus_dat_r $1\libresocsim_interface1_bank_bus_dat_r[7:0]
+      update \libresocsim_libresoc_constraintmanager_sdram_a $1\libresocsim_libresoc_constraintmanager_sdram_a[12:0]
   end
-  attribute \src "ls180.v:1146.11-1146.55"
-  process $proc$ls180.v:1146$2000
+  attribute \src "ls180.v:111.12-111.69"
+  process $proc$ls180.v:111$1564
     assign { } { }
-    assign $1\libresocsim_interface2_bank_bus_dat_r[7:0] 8'00000000
+    assign $1\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] 16'0000000000000000
     sync always
     sync init
-      update \libresocsim_interface2_bank_bus_dat_r $1\libresocsim_interface2_bank_bus_dat_r[7:0]
+      update \libresocsim_libresoc_constraintmanager_sdram_dq_o $1\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0]
   end
-  attribute \src "ls180.v:116.5-116.58"
-  process $proc$ls180.v:116$1563
+  attribute \src "ls180.v:112.5-112.62"
+  process $proc$ls180.v:112$1565
     assign { } { }
-    assign $1\libresocsim_libresoc_constraintmanager_uart_tx[0:0] 1'1
+    assign $1\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0] 1'0
     sync always
     sync init
-      update \libresocsim_libresoc_constraintmanager_uart_tx $1\libresocsim_libresoc_constraintmanager_uart_tx[0:0]
+      update \libresocsim_libresoc_constraintmanager_sdram_dq_oe $1\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0]
   end
-  attribute \src "ls180.v:1163.11-1163.55"
-  process $proc$ls180.v:1163$2001
+  attribute \src "ls180.v:1129.11-1129.55"
+  process $proc$ls180.v:1129$1999
     assign { } { }
-    assign $1\libresocsim_interface3_bank_bus_dat_r[7:0] 8'00000000
+    assign $1\libresocsim_interface1_bank_bus_dat_r[7:0] 8'00000000
     sync always
     sync init
-      update \libresocsim_interface3_bank_bus_dat_r $1\libresocsim_interface3_bank_bus_dat_r[7:0]
+      update \libresocsim_interface1_bank_bus_dat_r $1\libresocsim_interface1_bank_bus_dat_r[7:0]
   end
-  attribute \src "ls180.v:117.5-117.58"
-  process $proc$ls180.v:117$1564
+  attribute \src "ls180.v:113.5-113.61"
+  process $proc$ls180.v:113$1566
     assign { } { }
-    assign $0\libresocsim_libresoc_constraintmanager_uart_rx[0:0] 1'0
+    assign $1\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0] 1'0
     sync always
-      update \libresocsim_libresoc_constraintmanager_uart_rx $0\libresocsim_libresoc_constraintmanager_uart_rx[0:0]
     sync init
+      update \libresocsim_libresoc_constraintmanager_sdram_we_n $1\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0]
   end
-  attribute \src "ls180.v:1176.11-1176.55"
-  process $proc$ls180.v:1176$2002
+  attribute \src "ls180.v:114.5-114.62"
+  process $proc$ls180.v:114$1567
     assign { } { }
-    assign $1\libresocsim_interface4_bank_bus_dat_r[7:0] 8'00000000
+    assign $1\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0] 1'0
     sync always
     sync init
-      update \libresocsim_interface4_bank_bus_dat_r $1\libresocsim_interface4_bank_bus_dat_r[7:0]
+      update \libresocsim_libresoc_constraintmanager_sdram_ras_n $1\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0]
   end
-  attribute \src "ls180.v:118.12-118.66"
-  process $proc$ls180.v:118$1565
+  attribute \src "ls180.v:1146.11-1146.55"
+  process $proc$ls180.v:1146$2000
     assign { } { }
-    assign $1\libresocsim_libresoc_constraintmanager_sdram_a[12:0] 13'0000000000000
+    assign $1\libresocsim_interface2_bank_bus_dat_r[7:0] 8'00000000
     sync always
     sync init
-      update \libresocsim_libresoc_constraintmanager_sdram_a $1\libresocsim_libresoc_constraintmanager_sdram_a[12:0]
+      update \libresocsim_interface2_bank_bus_dat_r $1\libresocsim_interface2_bank_bus_dat_r[7:0]
   end
-  attribute \src "ls180.v:120.12-120.69"
-  process $proc$ls180.v:120$1566
+  attribute \src "ls180.v:115.5-115.62"
+  process $proc$ls180.v:115$1568
     assign { } { }
-    assign $1\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] 16'0000000000000000
+    assign $1\libresocsim_libresoc_constraintmanager_sdram_cas_n[0:0] 1'0
     sync always
     sync init
-      update \libresocsim_libresoc_constraintmanager_sdram_dq_o $1\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0]
+      update \libresocsim_libresoc_constraintmanager_sdram_cas_n $1\libresocsim_libresoc_constraintmanager_sdram_cas_n[0:0]
   end
-  attribute \src "ls180.v:121.5-121.62"
-  process $proc$ls180.v:121$1567
+  attribute \src "ls180.v:116.5-116.61"
+  process $proc$ls180.v:116$1569
     assign { } { }
-    assign $1\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0] 1'0
+    assign $1\libresocsim_libresoc_constraintmanager_sdram_cs_n[0:0] 1'0
     sync always
     sync init
-      update \libresocsim_libresoc_constraintmanager_sdram_dq_oe $1\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0]
+      update \libresocsim_libresoc_constraintmanager_sdram_cs_n $1\libresocsim_libresoc_constraintmanager_sdram_cs_n[0:0]
   end
-  attribute \src "ls180.v:1217.11-1217.55"
-  process $proc$ls180.v:1217$2003
+  attribute \src "ls180.v:1163.11-1163.55"
+  process $proc$ls180.v:1163$2001
     assign { } { }
-    assign $1\libresocsim_interface5_bank_bus_dat_r[7:0] 8'00000000
+    assign $1\libresocsim_interface3_bank_bus_dat_r[7:0] 8'00000000
     sync always
     sync init
-      update \libresocsim_interface5_bank_bus_dat_r $1\libresocsim_interface5_bank_bus_dat_r[7:0]
+      update \libresocsim_interface3_bank_bus_dat_r $1\libresocsim_interface3_bank_bus_dat_r[7:0]
   end
-  attribute \src "ls180.v:122.5-122.61"
-  process $proc$ls180.v:122$1568
+  attribute \src "ls180.v:117.5-117.60"
+  process $proc$ls180.v:117$1570
     assign { } { }
-    assign $1\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0] 1'0
+    assign $1\libresocsim_libresoc_constraintmanager_sdram_cke[0:0] 1'0
     sync always
     sync init
-      update \libresocsim_libresoc_constraintmanager_sdram_we_n $1\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0]
+      update \libresocsim_libresoc_constraintmanager_sdram_cke $1\libresocsim_libresoc_constraintmanager_sdram_cke[0:0]
   end
-  attribute \src "ls180.v:123.5-123.62"
-  process $proc$ls180.v:123$1569
+  attribute \src "ls180.v:1176.11-1176.55"
+  process $proc$ls180.v:1176$2002
     assign { } { }
-    assign $1\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0] 1'0
+    assign $1\libresocsim_interface4_bank_bus_dat_r[7:0] 8'00000000
     sync always
     sync init
-      update \libresocsim_libresoc_constraintmanager_sdram_ras_n $1\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0]
+      update \libresocsim_interface4_bank_bus_dat_r $1\libresocsim_interface4_bank_bus_dat_r[7:0]
   end
-  attribute \src "ls180.v:124.5-124.62"
-  process $proc$ls180.v:124$1570
+  attribute \src "ls180.v:118.11-118.65"
+  process $proc$ls180.v:118$1571
     assign { } { }
-    assign $1\libresocsim_libresoc_constraintmanager_sdram_cas_n[0:0] 1'0
+    assign $1\libresocsim_libresoc_constraintmanager_sdram_ba[1:0] 2'00
     sync always
     sync init
-      update \libresocsim_libresoc_constraintmanager_sdram_cas_n $1\libresocsim_libresoc_constraintmanager_sdram_cas_n[0:0]
+      update \libresocsim_libresoc_constraintmanager_sdram_ba $1\libresocsim_libresoc_constraintmanager_sdram_ba[1:0]
   end
-  attribute \src "ls180.v:125.5-125.61"
-  process $proc$ls180.v:125$1571
+  attribute \src "ls180.v:119.11-119.65"
+  process $proc$ls180.v:119$1572
     assign { } { }
-    assign $1\libresocsim_libresoc_constraintmanager_sdram_cs_n[0:0] 1'0
+    assign $1\libresocsim_libresoc_constraintmanager_sdram_dm[1:0] 2'00
     sync always
     sync init
-      update \libresocsim_libresoc_constraintmanager_sdram_cs_n $1\libresocsim_libresoc_constraintmanager_sdram_cs_n[0:0]
+      update \libresocsim_libresoc_constraintmanager_sdram_dm $1\libresocsim_libresoc_constraintmanager_sdram_dm[1:0]
   end
-  attribute \src "ls180.v:126.5-126.60"
-  process $proc$ls180.v:126$1572
+  attribute \src "ls180.v:120.5-120.62"
+  process $proc$ls180.v:120$1573
     assign { } { }
-    assign $1\libresocsim_libresoc_constraintmanager_sdram_cke[0:0] 1'0
+    assign $1\libresocsim_libresoc_constraintmanager_sdram_clock[0:0] 1'0
     sync always
     sync init
-      update \libresocsim_libresoc_constraintmanager_sdram_cke $1\libresocsim_libresoc_constraintmanager_sdram_cke[0:0]
+      update \libresocsim_libresoc_constraintmanager_sdram_clock $1\libresocsim_libresoc_constraintmanager_sdram_clock[0:0]
   end
-  attribute \src "ls180.v:127.11-127.65"
-  process $proc$ls180.v:127$1573
+  attribute \src "ls180.v:121.5-121.64"
+  process $proc$ls180.v:121$1574
     assign { } { }
-    assign $1\libresocsim_libresoc_constraintmanager_sdram_ba[1:0] 2'00
+    assign $0\libresocsim_libresoc_constraintmanager_spimaster_clk[0:0] 1'0
     sync always
+      update \libresocsim_libresoc_constraintmanager_spimaster_clk $0\libresocsim_libresoc_constraintmanager_spimaster_clk[0:0]
     sync init
-      update \libresocsim_libresoc_constraintmanager_sdram_ba $1\libresocsim_libresoc_constraintmanager_sdram_ba[1:0]
   end
-  attribute \src "ls180.v:128.11-128.65"
-  process $proc$ls180.v:128$1574
+  attribute \src "ls180.v:1217.11-1217.55"
+  process $proc$ls180.v:1217$2003
     assign { } { }
-    assign $1\libresocsim_libresoc_constraintmanager_sdram_dm[1:0] 2'00
+    assign $1\libresocsim_interface5_bank_bus_dat_r[7:0] 8'00000000
     sync always
     sync init
-      update \libresocsim_libresoc_constraintmanager_sdram_dm $1\libresocsim_libresoc_constraintmanager_sdram_dm[1:0]
+      update \libresocsim_interface5_bank_bus_dat_r $1\libresocsim_interface5_bank_bus_dat_r[7:0]
+  end
+  attribute \src "ls180.v:122.5-122.65"
+  process $proc$ls180.v:122$1575
+    assign { } { }
+    assign $0\libresocsim_libresoc_constraintmanager_spimaster_mosi[0:0] 1'0
+    sync always
+      update \libresocsim_libresoc_constraintmanager_spimaster_mosi $0\libresocsim_libresoc_constraintmanager_spimaster_mosi[0:0]
+    sync init
+  end
+  attribute \src "ls180.v:123.5-123.65"
+  process $proc$ls180.v:123$1576
+    assign { } { }
+    assign $0\libresocsim_libresoc_constraintmanager_spimaster_cs_n[0:0] 1'0
+    sync always
+      update \libresocsim_libresoc_constraintmanager_spimaster_cs_n $0\libresocsim_libresoc_constraintmanager_spimaster_cs_n[0:0]
+    sync init
   end
   attribute \src "ls180.v:1282.11-1282.55"
   process $proc$ls180.v:1282$2004
@@ -261325,13 +261341,13 @@ module \ls180
     sync init
       update \libresocsim_interface6_bank_bus_dat_r $1\libresocsim_interface6_bank_bus_dat_r[7:0]
   end
-  attribute \src "ls180.v:129.5-129.62"
-  process $proc$ls180.v:129$1575
+  attribute \src "ls180.v:130.12-130.65"
+  process $proc$ls180.v:130$1577
     assign { } { }
-    assign $1\libresocsim_libresoc_constraintmanager_sdram_clock[0:0] 1'0
+    assign $1\libresocsim_libresoc_constraintmanager_gpio_o[15:0] 16'0000000000000000
     sync always
     sync init
-      update \libresocsim_libresoc_constraintmanager_sdram_clock $1\libresocsim_libresoc_constraintmanager_sdram_clock[0:0]
+      update \libresocsim_libresoc_constraintmanager_gpio_o $1\libresocsim_libresoc_constraintmanager_gpio_o[15:0]
   end
   attribute \src "ls180.v:1307.11-1307.55"
   process $proc$ls180.v:1307$2005
@@ -261341,21 +261357,21 @@ module \ls180
     sync init
       update \libresocsim_interface7_bank_bus_dat_r $1\libresocsim_interface7_bank_bus_dat_r[7:0]
   end
-  attribute \src "ls180.v:131.12-131.65"
-  process $proc$ls180.v:131$1576
+  attribute \src "ls180.v:131.12-131.66"
+  process $proc$ls180.v:131$1578
     assign { } { }
-    assign $1\libresocsim_libresoc_constraintmanager_gpio_o[15:0] 16'0000000000000000
+    assign $1\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] 16'0000000000000000
     sync always
     sync init
-      update \libresocsim_libresoc_constraintmanager_gpio_o $1\libresocsim_libresoc_constraintmanager_gpio_o[15:0]
+      update \libresocsim_libresoc_constraintmanager_gpio_oe $1\libresocsim_libresoc_constraintmanager_gpio_oe[15:0]
   end
-  attribute \src "ls180.v:132.12-132.66"
-  process $proc$ls180.v:132$1577
+  attribute \src "ls180.v:132.5-132.58"
+  process $proc$ls180.v:132$1579
     assign { } { }
-    assign $1\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] 16'0000000000000000
+    assign $1\libresocsim_libresoc_constraintmanager_uart_tx[0:0] 1'1
     sync always
     sync init
-      update \libresocsim_libresoc_constraintmanager_gpio_oe $1\libresocsim_libresoc_constraintmanager_gpio_oe[15:0]
+      update \libresocsim_libresoc_constraintmanager_uart_tx $1\libresocsim_libresoc_constraintmanager_uart_tx[0:0]
   end
   attribute \src "ls180.v:1329.11-1329.35"
   process $proc$ls180.v:1329$2006
@@ -261365,12 +261381,12 @@ module \ls180
     sync init
       update \libresocsim_state $1\libresocsim_state[1:0]
   end
-  attribute \src "ls180.v:133.5-133.64"
-  process $proc$ls180.v:133$1578
+  attribute \src "ls180.v:133.5-133.58"
+  process $proc$ls180.v:133$1580
     assign { } { }
-    assign $0\libresocsim_libresoc_constraintmanager_spimaster_clk[0:0] 1'0
+    assign $0\libresocsim_libresoc_constraintmanager_uart_rx[0:0] 1'0
     sync always
-      update \libresocsim_libresoc_constraintmanager_spimaster_clk $0\libresocsim_libresoc_constraintmanager_spimaster_clk[0:0]
+      update \libresocsim_libresoc_constraintmanager_uart_rx $0\libresocsim_libresoc_constraintmanager_uart_rx[0:0]
     sync init
   end
   attribute \src "ls180.v:1330.11-1330.40"
@@ -261453,14 +261469,6 @@ module \ls180
     sync init
       update \rhs_array_muxed2 $1\rhs_array_muxed2[1:0]
   end
-  attribute \src "ls180.v:134.5-134.65"
-  process $proc$ls180.v:134$1579
-    assign { } { }
-    assign $0\libresocsim_libresoc_constraintmanager_spimaster_mosi[0:0] 1'0
-    sync always
-      update \libresocsim_libresoc_constraintmanager_spimaster_mosi $0\libresocsim_libresoc_constraintmanager_spimaster_mosi[0:0]
-    sync init
-  end
   attribute \src "ls180.v:1340.5-1340.28"
   process $proc$ls180.v:1340$2017
     assign { } { }
@@ -261541,14 +261549,6 @@ module \ls180
     sync init
       update \rhs_array_muxed9 $1\rhs_array_muxed9[0:0]
   end
-  attribute \src "ls180.v:135.5-135.65"
-  process $proc$ls180.v:135$1580
-    assign { } { }
-    assign $0\libresocsim_libresoc_constraintmanager_spimaster_cs_n[0:0] 1'0
-    sync always
-      update \libresocsim_libresoc_constraintmanager_spimaster_cs_n $0\libresocsim_libresoc_constraintmanager_spimaster_cs_n[0:0]
-    sync init
-  end
   attribute \src "ls180.v:1350.5-1350.29"
   process $proc$ls180.v:1350$2027
     assign { } { }
diff --git a/pinmux b/pinmux
index f6c9eb0..f200b5c 160000
--- a/pinmux
+++ b/pinmux
@@ -1 +1 @@
-Subproject commit f6c9eb0ff8144658e83ea9665c23ce57905ea61e
+Subproject commit f200b5cb8ecb2bf5cde04e6aa9cb39ca6c2d908e