From: lkcl <lkcl@web>
Date: Mon, 22 May 2023 15:04:13 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4e934bc81a29d87ba364a9f94ba3d0399ff4d153;p=libreriscv.git

---

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 5932e4946..c3d2362d1 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -121,7 +121,8 @@ must also raise illegal instruction traps in order to allow emulation.
 Unless otherwise stated, reserved values are always all zeros.
 
 This is unlike OpenPower ISA v3.1, which in many instances does not
-require a trap if reserved fields are nonzero.  Where the standard Power
+require a trap if reserved fields are nonzero, instead relying on software
+to avoid use of such fields.  Where the standard Power
 ISA definition is intended the red keyword `RESERVED` is used.
 
 ##  Definition of "UnVectoriseable"