From: Kenneth Graunke <kenneth@whitecape.org>
Date: Tue, 10 Dec 2013 09:21:54 +0000 (-0800)
Subject: i965: Disassemble UV types, not UB types.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4e95a099373c7e3f3f5f0f2854bc4eb582724a0a;p=mesa.git

i965: Disassemble UV types, not UB types.

UB types have never been supported as immediates.  On Gen4-5, register
encoding 4 is "Reserved."  On Gen6+, it means UV.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
---

diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c
index ade7e7fcc54..4c435beaa3b 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -900,8 +900,8 @@ static int imm (FILE *file, unsigned type, struct brw_instruction *inst) {
     case BRW_REGISTER_TYPE_W:
 	format (file, "%dW", (int16_t) inst->bits3.d);
 	break;
-    case BRW_REGISTER_TYPE_UB:
-	format (file, "0x%02xUB", (int8_t) inst->bits3.ud);
+    case BRW_REGISTER_TYPE_UV:
+	format (file, "0x%08xUV", inst->bits3.ud);
 	break;
     case BRW_REGISTER_TYPE_VF:
 	format (file, "Vector Float");